From: Neil Armstrong <neil.armstrong@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Neil Armstrong <neil.armstrong@linaro.org>
Subject: [PATCH 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties
Date: Wed, 28 Jan 2026 11:33:17 +0100 [thread overview]
Message-ID: <20260128-topic-sm8650-upstream-cpu-props-v1-2-9fbb5efe7f07@linaro.org> (raw)
In-Reply-To: <20260128-topic-sm8650-upstream-cpu-props-v1-0-9fbb5efe7f07@linaro.org>
Add the L1 cache size and its line size (cache-size and
cache-line-size) with the corresponding L1-I cache and L1-D cache.
L1 cache is unified, but clidr_el1 register (get_cache_type) tells that
L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and
d-cache-line-size and cache-line-size of L3 cache is specified.
All cache line sizes were confirmed by checking ccsidr_el1.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 56 ++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 8671c25dd68f..f8563ec79dc6 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -75,6 +75,11 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a520";
reg = <0 0>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+
clocks = <&cpufreq_hw 0>;
power-domains = <&cpu_pd0>;
@@ -103,11 +108,15 @@ l2_0: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
+ cache-size = <12582912>;
+ cache-line-size = <64>;
};
};
};
@@ -117,6 +126,11 @@ cpu1: cpu@100 {
compatible = "arm,cortex-a520";
reg = <0 0x100>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+
clocks = <&cpufreq_hw 0>;
power-domains = <&cpu_pd1>;
@@ -146,6 +160,11 @@ cpu2: cpu@200 {
compatible = "arm,cortex-a720";
reg = <0 0x200>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd2>;
@@ -174,6 +193,8 @@ l2_200: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
+ cache-size = <524288>;
+ cache-line-size = <64>;
};
};
@@ -182,6 +203,11 @@ cpu3: cpu@300 {
compatible = "arm,cortex-a720";
reg = <0 0x300>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd3>;
@@ -210,6 +236,8 @@ l2_300: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
+ cache-size = <524288>;
+ cache-line-size = <64>;
};
};
@@ -218,6 +246,11 @@ cpu4: cpu@400 {
compatible = "arm,cortex-a720";
reg = <0 0x400>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd4>;
@@ -246,6 +279,8 @@ l2_400: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
+ cache-size = <524288>;
+ cache-line-size = <64>;
};
};
@@ -254,6 +289,11 @@ cpu5: cpu@500 {
compatible = "arm,cortex-a720";
reg = <0 0x500>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+
clocks = <&cpufreq_hw 1>;
power-domains = <&cpu_pd5>;
@@ -282,6 +322,8 @@ l2_500: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
+ cache-size = <524288>;
+ cache-line-size = <64>;
};
};
@@ -290,6 +332,11 @@ cpu6: cpu@600 {
compatible = "arm,cortex-a720";
reg = <0 0x600>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+
clocks = <&cpufreq_hw 1>;
power-domains = <&cpu_pd6>;
@@ -318,6 +365,8 @@ l2_600: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
+ cache-size = <524288>;
+ cache-line-size = <64>;
};
};
@@ -326,6 +375,11 @@ cpu7: cpu@700 {
compatible = "arm,cortex-x4";
reg = <0 0x700>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+
clocks = <&cpufreq_hw 2>;
power-domains = <&cpu_pd7>;
@@ -354,6 +408,8 @@ l2_700: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
};
};
--
2.34.1
next prev parent reply other threads:[~2026-01-28 10:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 10:33 [PATCH 0/3] arm64: qcom: sm8650: misc enhancements Neil Armstrong
2026-01-28 10:33 ` [PATCH 1/3] arm64: dts: qcom: sm8650: update the cpus capacity-dmips-mhz Neil Armstrong
2026-01-28 12:17 ` Konrad Dybcio
2026-01-28 10:33 ` Neil Armstrong [this message]
2026-01-28 10:46 ` [PATCH 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties Konrad Dybcio
2026-01-28 13:53 ` Neil Armstrong
2026-01-28 10:33 ` [PATCH 3/3] arm64: dts: qcom: sm8650: fix soundwire ports properties Neil Armstrong
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