Re: [PATCH 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 1/28/26 11:33 AM, Neil Armstrong wrote:
> Add the L1 cache size and its line size (cache-size and
> cache-line-size) with the corresponding L1-I cache and L1-D cache.
> 
> L1 cache is unified, but clidr_el1 register (get_cache_type) tells that
> L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and
> d-cache-line-size and cache-line-size of L3 cache is specified.
> 
> All cache line sizes were confirmed by checking ccsidr_el1.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8650.dtsi | 56 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 8671c25dd68f..f8563ec79dc6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -75,6 +75,11 @@ cpu0: cpu@0 {
>  			compatible = "arm,cortex-a520";
>  			reg = <0 0>;
>  
> +			i-cache-size = <65536>;
> +			i-cache-line-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-line-size = <64>;
> +
>  			clocks = <&cpufreq_hw 0>;
>  
>  			power-domains = <&cpu_pd0>;
> @@ -103,11 +108,15 @@ l2_0: l2-cache {
>  				cache-level = <2>;
>  				cache-unified;
>  				next-level-cache = <&l3_0>;
> +				cache-size = <262144>;

This should be 512 kiB, shared for c0/1, according to a block
diagram

Everything else lgtm, although I can't find a source for the
cache*line* sizes

Konrad