From: Peter Zijlstra <peterz@infradead.org>
To: Thomas Gleixner <tglx@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
Ihor Solodrai <ihor.solodrai@linux.dev>,
Shrikanth Hegde <sshegde@linux.ibm.com>,
Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
Michael Jeanson <mjeanson@efficios.com>
Subject: Re: [patch V2 0/4] sched/mmcid: Cure mode transition woes
Date: Mon, 2 Feb 2026 11:14:24 +0100 [thread overview]
Message-ID: <20260202101424.GB3016024@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20260201192234.380608594@kernel.org>
On Mon, Feb 02, 2026 at 10:39:35AM +0100, Thomas Gleixner wrote:
> --- a/kernel/sched/core.c
> +++ b/kernel/sched/core.c
> @@ -10445,6 +10445,12 @@ static bool mm_update_max_cids(struct mm
>
> /* Flip the mode and set the transition flag to bridge the transfer */
> WRITE_ONCE(mc->mode, mc->mode ^ (MM_CID_TRANSIT | MM_CID_ONCPU));
> + /*
> + * Order the store against the subsequent fixups so that
> + * acquire(rq::lock) cannot be reordered by the CPU before the
> + * store.
> + */
> + smp_mb();
> return true;
> }
>
> @@ -10487,6 +10493,16 @@ static inline void mm_update_cpus_allowe
> irq_work_queue(&mc->irq_work);
> }
>
> +static inline void mm_cid_complete_transit(struct mm_struct *mm, unsigned int mode)
> +{
> + /*
> + * Ensure that the store removing the TRANSIT bit cannot be
> + * reordered by the CPU before the fixups have been completed.
> + */
> + smp_mb();
> + WRITE_ONCE(mm->mm_cid.mode, mode);
> +}
I think this could've been smp_store_release(), but this is the slow
path so nobody cares and this is nicely symmetric.
next prev parent reply other threads:[~2026-02-02 10:14 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-02 9:39 Thomas Gleixner
2026-02-02 9:39 ` [patch V2 1/4] sched/mmcid: Prevent live lock on task to CPU mode transition Thomas Gleixner
2026-02-02 14:50 ` Mathieu Desnoyers
2026-02-04 13:27 ` [tip: sched/urgent] " tip-bot2 for Thomas Gleixner
2026-02-02 9:39 ` [patch V2 2/4] sched/mmcid: Protect transition on weakly ordered systems Thomas Gleixner
2026-02-02 14:53 ` Mathieu Desnoyers
2026-02-04 13:27 ` [tip: sched/urgent] " tip-bot2 for Thomas Gleixner
2026-02-02 9:39 ` [patch V2 3/4] sched/mmcid: Drop per CPU CID immediately when switching to per task mode Thomas Gleixner
2026-02-04 13:27 ` [tip: sched/urgent] " tip-bot2 for Thomas Gleixner
2026-02-10 7:33 ` [patch V2 3/4] " Shinichiro Kawasaki
2026-02-10 10:44 ` Thomas Gleixner
2026-02-10 11:51 ` Shinichiro Kawasaki
2026-02-10 13:03 ` Peter Zijlstra
2026-02-10 14:15 ` Shinichiro Kawasaki
2026-02-10 13:33 ` Thomas Gleixner
2026-02-10 14:55 ` Shinichiro Kawasaki
2026-02-10 16:20 ` [PATCH] sched/mmcid: Don't assume CID is CPU owned on mode switch Thomas Gleixner
2026-02-10 16:28 ` Mathieu Desnoyers
2026-02-11 10:33 ` Takashi Iwai
2026-02-11 21:00 ` Linus Torvalds
2026-02-02 9:39 ` [patch V2 4/4] sched/mmcid: Optimize transitional CIDs when scheduling out Thomas Gleixner
2026-02-02 14:56 ` Mathieu Desnoyers
2026-02-04 13:27 ` [tip: sched/urgent] " tip-bot2 for Thomas Gleixner
2026-02-02 10:14 ` Peter Zijlstra [this message]
2026-02-02 11:46 ` [patch V2 0/4] sched/mmcid: Cure mode transition woes Mathieu Desnoyers
2026-02-02 12:54 ` Peter Zijlstra
2026-02-02 21:22 ` Mathieu Desnoyers
2026-02-04 10:53 ` Thomas Gleixner
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