Re: [patch V2 0/4] sched/mmcid: Cure mode transition woes

[Mathieu Desnoyers <mathieu.desnoyers@efficios.com>]

On 2026-02-02 05:14, Peter Zijlstra wrote:
> On Mon, Feb 02, 2026 at 10:39:35AM +0100, Thomas Gleixner wrote:
> 
>> --- a/kernel/sched/core.c
>> +++ b/kernel/sched/core.c
>> @@ -10445,6 +10445,12 @@ static bool mm_update_max_cids(struct mm
>>   
>>   	/* Flip the mode and set the transition flag to bridge the transfer */
>>   	WRITE_ONCE(mc->mode, mc->mode ^ (MM_CID_TRANSIT | MM_CID_ONCPU));
>> +	/*
>> +	 * Order the store against the subsequent fixups so that
>> +	 * acquire(rq::lock) cannot be reordered by the CPU before the
>> +	 * store.
>> +	 */
>> +	smp_mb();
>>   	return true;
>>   }
>>   
>> @@ -10487,6 +10493,16 @@ static inline void mm_update_cpus_allowe
>>   	irq_work_queue(&mc->irq_work);
>>   }
>>   
>> +static inline void mm_cid_complete_transit(struct mm_struct *mm, unsigned int mode)
>> +{
>> +	/*
>> +	 * Ensure that the store removing the TRANSIT bit cannot be
>> +	 * reordered by the CPU before the fixups have been completed.
>> +	 */
>> +	smp_mb();
>> +	WRITE_ONCE(mm->mm_cid.mode, mode);
>> +}
> 
> I think this could've been smp_store_release(), but this is the slow
> path so nobody cares and this is nicely symmetric.

I'm not sure the store-release would work here. What load-acquire
would it pair with ?

Thanks,

Mathieu

-- 
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com