[PATCH v2 0/7] perf/amd/ibs: Future enhancements

[Ravi Bangoria <ravi.bangoria@amd.com>]

Add support for new capabilities that will appear in future AMD
CPUs:
  - Alternate disable bit with control only MSRs to eliminate the
    RMW race in existing IBS_{FETCH|OP}_CTL MSRs
  - RIP bit 63 filtering, which can be used as hardware assisted
    privilege filtering, enabling IBS for unprivileged users without
    software based privilege filtering
  - Fetch latency threshold filter to capture only high-latency fetch
    events
  - Streaming-store filter to sample only instructions that perform
    streaming stores
  - Remote socket indicator for load/store instructions

Patches are prepared on tip/perf/core (7db06e329af3) + IBS fixes series

IBS fixes series:
  https://lore.kernel.org/r/20260216042216.1440-1-ravi.bangoria@amd.com

Perf tools patches:
  https://lore.kernel.org/r/20260119024328.897-1-ravi.bangoria@amd.com

v1: https://lore.kernel.org/r/20260116033450.965-1-ravi.bangoria@amd.com
v1->v2:
  - Split fixes series from future enhancements
  - Replace magic numbers with macros

Ravi Bangoria (7):
  perf/amd/ibs: Define macro for ldlat mask and shift
  perf/amd/ibs: Add new MSRs and CPUID bits definitions
  perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to eliminate RMW race
  perf/amd/ibs: Enable fetch latency filtering
  perf/amd/ibs: Enable RIP bit63 hardware filtering
  perf/amd/ibs: Enable streaming store filter
  perf/amd/ibs: Advertise remote socket capability

 arch/x86/events/amd/ibs.c         | 238 ++++++++++++++++++++++++++++--
 arch/x86/include/asm/amd/ibs.h    |   4 +-
 arch/x86/include/asm/msr-index.h  |   2 +
 arch/x86/include/asm/perf_event.h |  55 ++++---
 4 files changed, 266 insertions(+), 33 deletions(-)

-- 
2.43.0