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From: Yao Zi <me@ziyao.cc>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Siddharth Vadapalli" <s-vadapalli@ti.com>,
	"Hans Zhang" <18255117159@163.com>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Chen Wang" <unicorn_wang@outlook.com>,
	"Manikandan K Pillai" <mpillai@cadence.com>,
	"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>,
	"Inochi Amaoto" <inochiama@gmail.com>,
	"Han Gao" <rabenda.cn@gmail.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Yao Zi <me@ziyao.cc>
Subject: [PATCH v2 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports
Date: Fri, 27 Feb 2026 18:19:23 +0000	[thread overview]
Message-ID: <20260227181925.52475-1-me@ziyao.cc> (raw)

After talking to Inochi privately, I'll take the patch instead.

This series defines initialization/de-initialization hooks for Cadence
PCIe host driver to allow platform drivers to override RC ports
properties, and provides such an initialization hook in SG2042 PCIe
driver to clear PCI_EXP_LNKCAP_ASPMS since SG2042's implementation is
broken.

I've considered to re-write LNKCAP after cdns_pcie_host_setup(), like
what has been done in the previous version of patch. However,
cdns_pcie_host_setup() performs pci_host_probe(), which finally invokes
set_pcie_port_type() on the root port. It reads ASPM-related LNKCAP,
which might lead to dangling pci_dev.aspm_{l0s,l1}_support values.
Early PCI device fixup won't work for similar reasons, since the fixup
is performed in pci_setup_device() after calling set_pcie_port_type().

It's hard to fix up the LNKCAP earlier than invokation of
cdns_pcie_host_setup() in SG2042's PCIe driver, either, since
the function also performs resource allocation/mapping, and we have no
access to the RC registers before it returns.

The safest solution which also depends on no PCI subsystem
implementation detail is to have the LNKCAP fixed up right before
informing the PCI subsystem of the device through pci_host_probe(), so
here come the platform-specific hooks.

Changed from v1:
- Disable L0s/L1 capabilities through LNKCAP instead of LNKCTL
- Introduce platform-specific init/deinit hooks (new PATCH 1) to
  realiably overwrite PCIe RC properties
- Link to v1: https://lore.kernel.org/all/20260109040756.731169-2-inochiama@gmail.com/

Changed from the original patch:
- Use driver to mask the ASPM advertisement
- Separate from the following patch
  https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com

Yao Zi (2):
  PCI: cadence: Support platform-specific hooks for RC init/deinit
  PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

 .../controller/cadence/pcie-cadence-host.c    |  8 +++++++-
 drivers/pci/controller/cadence/pcie-cadence.h |  7 +++++++
 drivers/pci/controller/cadence/pcie-sg2042.c  | 20 +++++++++++++++++++
 3 files changed, 34 insertions(+), 1 deletion(-)

-- 
2.53.0


             reply	other threads:[~2026-02-27 18:20 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-27 18:19 Yao Zi [this message]
2026-02-27 18:19 ` [PATCH v2 1/2] PCI: cadence: Support platform-specific hooks for RC init/deinit Yao Zi
2026-03-03  1:08   ` Inochi Amaoto
2026-03-03  6:34   ` Chen Wang
2026-02-27 18:19 ` [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports Yao Zi
2026-02-27 18:24   ` Yao Zi
2026-03-03  1:09     ` Inochi Amaoto
2026-03-03  6:37   ` Chen Wang
2026-03-26 16:45   ` Manivannan Sadhasivam
2026-03-27  8:19     ` Yao Zi
2026-04-02 12:26       ` Chen Wang

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