Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Chen Wang <unicorn_wang@outlook.com>]

On 2/28/2026 2:19 AM, Yao Zi wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
>
> Provide a platform-specific initialization hook to override the L0s and
> L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> doesn't try to enable those states.
>
> Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> Co-authored-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Yao Zi <me@ziyao.cc>
> ---
>   drivers/pci/controller/cadence/pcie-sg2042.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
> index 0c50c74d03ee..3142f82bd393 100644
> --- a/drivers/pci/controller/cadence/pcie-sg2042.c
> +++ b/drivers/pci/controller/cadence/pcie-sg2042.c
> @@ -32,6 +32,25 @@ static struct pci_ops sg2042_pcie_child_ops = {
>   	.write		= pci_generic_config_write,
>   };
>   
> +static int sg2042_pcie_disable_l0s_l1(struct cdns_pcie_rc *rc)
> +{
> +	struct cdns_pcie *pcie = &rc->pcie;
> +	u32 pcie_lnkcap_off;
> +	u32 lnkcap;
> +
> +	pcie_lnkcap_off = CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP;
> +
> +	lnkcap = cdns_pcie_rp_readw(pcie, pcie_lnkcap_off);
> +	lnkcap &= ~PCI_EXP_LNKCAP_ASPMS;
> +	cdns_pcie_rp_writew(pcie, pcie_lnkcap_off, lnkcap);
> +
> +	return 0;
> +}
> +
> +static const struct cdns_pcie_rc_ops sg2042_pcie_rc_ops = {
> +	.init	= sg2042_pcie_disable_l0s_l1,
> +};
> +
>   static int sg2042_pcie_probe(struct platform_device *pdev)
>   {
>   	struct device *dev = &pdev->dev;
> @@ -48,6 +67,7 @@ static int sg2042_pcie_probe(struct platform_device *pdev)
>   	bridge->child_ops = &sg2042_pcie_child_ops;
>   
>   	rc = pci_host_bridge_priv(bridge);
> +	rc->ops = &sg2042_pcie_rc_ops;
>   	pcie = &rc->pcie;
>   	pcie->dev = dev;
>   
LGTM.

Reviewd-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>

Thanks,

Chen