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From: Peter Zijlstra <peterz@infradead.org>
To: Ian Rogers <irogers@google.com>
Cc: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>,
	Breno Leitao <leitao@debian.org>, Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>,
	Adrian Hunter <adrian.hunter@intel.com>,
	James Clark <james.clark@linaro.org>,
	Thomas Gleixner <tglx@kernel.org>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	kernel-team@meta.com, stable@vger.kernel.org
Subject: Re: [PATCH v2] perf/x86: Move event pointer setup earlier in x86_pmu_enable()
Date: Wed, 11 Mar 2026 18:35:09 +0100	[thread overview]
Message-ID: <20260311173509.GR606826@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <CAP-5=fWAzaKNO0wmAA89ovJLFgxCWQ3khnyWFotnaSAGiugv+A@mail.gmail.com>

On Wed, Mar 11, 2026 at 09:37:08AM -0700, Ian Rogers wrote:

> Fwiw, an AI review was saying something similar to me. 

How do you guys get this AI stuff to say anything sensible at all about
the code? Every time I try, it is telling me the most abject nonsense.
I've wasted hours of my life trying to guide it to known bugs, in vain.

> I wonder if the
> issue with NMI storms exists already via another path:
> 
> By populating cpuc->events[idx] here, even for events that skip
> x86_pmu_start() due to the PERF_HES_ARCH check, can this lead to PEBS
> data corruption?
> 
> For Intel PEBS, intel_pmu_pebs_late_setup() iterates over cpuc->event_list
> and enables PEBS_DATA_CFG for this counter index regardless of its stopped
> state. If the PMU hardware generates PEBS records for this uninitialized
> counter, or if there are leftover PEBS records from the counter's previous
> occupant (since x86_pmu_stop() does not drain the PEBS buffer),
> intel_perf_event_update_pmc() will now find a non-NULL event pointer.
> Will it incorrectly process these leftover records and attribute them
> to the stopped event?

Yes.

> Additionally, does this change leave the unthrottled event's hardware
> counter uninitialized?

Also yes.

> When x86_pmu_enable() moves a throttled event to a new counter, it sets
> PERF_HES_ARCH and skips calling x86_pmu_start(event, PERF_EF_RELOAD).
> Later, when the timer tick unthrottles the event, it calls
> perf_event_unthrottle(), which invokes event->pmu->start(event, 0).
> In x86_pmu_start(), because flags == 0 (lacking PERF_EF_RELOAD),
> x86_pmu_set_period() is skipped. Will the newly assigned hardware counter
> be enabled without being programmed with the event's period, potentially
> causing it to start from a garbage value and leading to incorrect sampling
> intervals or NMI storms?

Don't think you can get NMI storms this way. If the PMI trips, we'll do
set_period and that should fix it up.

So just wrong counting.

  reply	other threads:[~2026-03-11 17:35 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-10 10:13 Breno Leitao
2026-03-11  2:04 ` Mi, Dapeng
2026-03-11 16:37   ` Ian Rogers
2026-03-11 17:35     ` Peter Zijlstra [this message]
2026-03-11 20:40       ` Peter Zijlstra
2026-03-12  2:53         ` Mi, Dapeng
2026-03-13 13:23           ` Breno Leitao
2026-03-13 15:35             ` Peter Zijlstra
2026-03-13 16:57               ` Breno Leitao
2026-03-16  9:50         ` [tip: perf/urgent] x86/perf: Make sure to program the counter value for stopped events on migration tip-bot2 for Peter Zijlstra
2026-03-12  1:46       ` [PATCH v2] perf/x86: Move event pointer setup earlier in x86_pmu_enable() Mi, Dapeng
2026-03-11 17:18   ` Peter Zijlstra
2026-03-12  1:05     ` Mi, Dapeng
2026-03-16  9:50 ` [tip: perf/urgent] " tip-bot2 for Breno Leitao

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