From: Sumit Kumar <sumit.kumar@oss.qualcomm.com>
To: "Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
"Veerabhadrarao Badiganti"
<veerabhadrarao.badiganti@oss.qualcomm.com>,
"Subramanian Ananthanarayanan"
<subramanian.ananthanarayanan@oss.qualcomm.com>,
"Akhil Vinod" <akhil.vinod@oss.qualcomm.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Marek Szyprowski" <m.szyprowski@samsung.com>,
"Robin Murphy" <robin.murphy@arm.com>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>
Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
iommu@lists.linux.dev, linux-pci@vger.kernel.org,
mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org,
Sumit Kumar <sumit.kumar@oss.qualcomm.com>
Subject: [PATCH 0/3] dmaengine: Add batched scatter-gather DMA support
Date: Fri, 13 Mar 2026 12:19:24 +0530 [thread overview]
Message-ID: <20260313-dma_multi_sg-v1-0-8fabb0d1a759@oss.qualcomm.com> (raw)
Synopsys DesignWare eDMA IP supports a linked-list (LL) mode where
each LL item carries independent source and destination addresses. This
allows multiple independent memory transfers to be described in a single
linked list and submitted to the hardware as one DMA transaction, without
any CPU intervention between items. The IP processes LL items strictly
in order, guaranteeing that scatter-gather entries are never reordered.
This series leverages that hardware capability to introduce a new
dmaengine API — dmaengine_prep_batch_sg_dma() — for batching multiple
independent buffers into a single DMA transaction. Each scatter-gather
entry specifies both its own source (dma_address) and destination
(dma_dst_address), enabling the eDMA hardware to process them as a
single linked-list transaction.
The primary use case is MHI endpoint ring caching. When an MHI ring
wraps around, data spans two non-contiguous memory regions (tail and
head portions). Previously this required two separate DMA transactions
with two interrupts. With this series, both regions are submitted as a
single batched transaction, reducing submission overhead and interrupt
count.
The series includes:
1. Core DMA engine API and DW eDMA driver implementation
2. PCI EPF MHI driver support for batched transfers
3. MHI endpoint ring caching optimization using batched reads
Performance Benefits:
--------------------
- Reduced DMA submission overhead for multiple transfers
- Better hardware utilization through batched operations
- Lower latency for ring wraparound scenarios
Signed-off-by: Sumit Kumar <sumit.kumar@oss.qualcomm.com>
---
Sumit Kumar (3):
dmaengine: Add multi-buffer support in single DMA transfer
PCI: epf-mhi: Add batched DMA read support
bus: mhi: ep: Use batched read for ring caching
drivers/bus/mhi/ep/ring.c | 43 +++++-----
drivers/dma/dw-edma/Kconfig | 1 +
drivers/dma/dw-edma/dw-edma-core.c | 40 ++++++++-
drivers/dma/dw-edma/dw-edma-core.h | 3 +-
drivers/pci/endpoint/functions/Kconfig | 1 +
drivers/pci/endpoint/functions/pci-epf-mhi.c | 120 +++++++++++++++++++++++++++
include/linux/dmaengine.h | 29 ++++++-
include/linux/mhi_ep.h | 3 +
include/linux/scatterlist.h | 7 ++
kernel/dma/Kconfig | 3 +
10 files changed, 224 insertions(+), 26 deletions(-)
---
base-commit: f0b9d8eb98dfee8d00419aa07543bdc2c1a44fb1
change-id: 20260108-dma_multi_sg-c217650373c2
Best regards,
--
Sumit Kumar <sumit.kumar@oss.qualcomm.com>
next reply other threads:[~2026-03-13 6:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 6:49 Sumit Kumar [this message]
2026-03-13 6:49 ` [PATCH 1/3] dmaengine: Add multi-buffer support in single DMA transfer Sumit Kumar
2026-03-13 15:16 ` Robin Murphy
2026-03-16 17:05 ` Niklas Cassel
2026-03-17 10:54 ` Vinod Koul
2026-03-30 5:28 ` Sumit Kumar
2026-03-13 6:49 ` [PATCH 2/3] PCI: epf-mhi: Add batched DMA read support Sumit Kumar
2026-03-13 6:49 ` [PATCH 3/3] bus: mhi: ep: Use batched read for ring caching Sumit Kumar
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