* [PATCH V8 01/13] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 2:08 ` [PATCH V8 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties Sherry Sun
` (11 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property
for the Root Port node.
The reset-gpios property is already defined in pci-bus-common.yaml for
PERST#, so use it instead of the local reset-gpio property. Keep the
existing reset-gpio property in the bridge node for backward
compatibility, but mark it as deprecated.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 12a01f7a5744..d1a2526f43dc 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -59,16 +59,34 @@ properties:
- const: dma
reset-gpio:
+ deprecated: true
description: Should specify the GPIO for controlling the PCI bus device
reset signal. It's not polarity aware and defaults to active-low reset
sequence (L=reset state, H=operation state) (optional required).
+ This property is deprecated, instead of referencing this property from the
+ host bridge node, use the reset-gpios property from the root port node.
reset-gpio-active-high:
+ deprecated: true
description: If present then the reset sequence using the GPIO
specified in the "reset-gpio" property is reversed (H=reset state,
L=operation state) (optional required).
+ This property is deprecated along with the reset-gpio property above, use
+ the reset-gpios property from the root port node.
type: boolean
+ pcie@0:
+ description:
+ Describe the i.MX6 PCIe Root Port.
+ type: object
+ $ref: /schemas/pci/pci-pci-bridge.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+
+ unevaluatedProperties: false
+
required:
- compatible
- reg
@@ -229,6 +247,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
+ #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pcie: pcie@1ffc000 {
@@ -255,5 +274,18 @@ examples:
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
+
+ pcie_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ };
};
...
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V8 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
2026-03-13 2:08 ` [PATCH V8 01/13] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-16 5:40 ` Manivannan Sadhasivam
2026-03-13 2:08 ` [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in dw_pcie_host_init() Sherry Sun
` (10 subsequent siblings)
12 siblings, 1 reply; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Introduce generic helper functions to parse Root Port device tree nodes
and extract common properties like reset GPIOs. This allows multiple
PCI host controller drivers to share the same parsing logic.
Define struct pci_host_port to hold common Root Port properties
(currently only reset GPIO descriptor) and add
pci_host_common_parse_ports() to parse Root Port nodes from device tree.
Also add the 'ports' list to struct pci_host_bridge for better maintain
parsed Root Port information.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
drivers/pci/controller/pci-host-common.c | 78 ++++++++++++++++++++++++
drivers/pci/controller/pci-host-common.h | 15 +++++
drivers/pci/probe.c | 1 +
include/linux/pci.h | 1 +
4 files changed, 95 insertions(+)
diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c
index d6258c1cffe5..2f012cf80463 100644
--- a/drivers/pci/controller/pci-host-common.c
+++ b/drivers/pci/controller/pci-host-common.c
@@ -9,6 +9,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/gpio/consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
@@ -17,6 +18,83 @@
#include "pci-host-common.h"
+/**
+ * pci_host_common_delete_ports - Cleanup function for port list
+ * @data: Pointer to the port list head
+ */
+static void pci_host_common_delete_ports(void *data)
+{
+ struct list_head *ports = data;
+ struct pci_host_port *port, *tmp;
+
+ list_for_each_entry_safe(port, tmp, ports, list)
+ list_del(&port->list);
+}
+
+/**
+ * pci_host_common_parse_port - Parse a single Root Port node
+ * @dev: Device pointer
+ * @bridge: PCI host bridge
+ * @node: Device tree node of the Root Port
+ *
+ * Returns: 0 on success, negative error code on failure
+ */
+static int pci_host_common_parse_port(struct device *dev,
+ struct pci_host_bridge *bridge,
+ struct device_node *node)
+{
+ struct pci_host_port *port;
+ struct gpio_desc *reset;
+
+ reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
+ "reset", GPIOD_ASIS, "PERST#");
+ if (IS_ERR(reset))
+ return PTR_ERR(reset);
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ port->reset = reset;
+ INIT_LIST_HEAD(&port->list);
+ list_add_tail(&port->list, &bridge->ports);
+
+ return 0;
+}
+
+/**
+ * pci_host_common_parse_ports - Parse Root Port nodes from device tree
+ * @dev: Device pointer
+ * @bridge: PCI host bridge
+ *
+ * This function iterates through child nodes of the host bridge and parses
+ * Root Port properties (currently only reset GPIO).
+ *
+ * Returns: 0 on success, -ENOENT if no ports found, other negative error codes
+ * on failure
+ */
+int pci_host_common_parse_ports(struct device *dev, struct pci_host_bridge *bridge)
+{
+ int ret = -ENOENT;
+ int err;
+
+ for_each_available_child_of_node_scoped(dev->of_node, of_port) {
+ if (!of_node_is_type(of_port, "pci"))
+ continue;
+ ret = pci_host_common_parse_port(dev, bridge, of_port);
+ if (ret)
+ return ret;
+ }
+
+ err = devm_add_action_or_reset(dev, pci_host_common_delete_ports,
+ &bridge->ports);
+ if (err)
+ return err;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_host_common_parse_ports);
+
static void gen_pci_unmap_cfg(void *ptr)
{
pci_ecam_free((struct pci_config_window *)ptr);
diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/controller/pci-host-common.h
index b5075d4bd7eb..1de015d10b9f 100644
--- a/drivers/pci/controller/pci-host-common.h
+++ b/drivers/pci/controller/pci-host-common.h
@@ -12,6 +12,21 @@
struct pci_ecam_ops;
+/**
+ * struct pci_host_port - Generic Root Port properties
+ * @list: List node for linking multiple ports
+ * @reset: GPIO descriptor for PERST# signal
+ *
+ * This structure contains common properties that can be parsed from
+ * Root Port device tree nodes.
+ */
+struct pci_host_port {
+ struct list_head list;
+ struct gpio_desc *reset;
+};
+
+int pci_host_common_parse_ports(struct device *dev, struct pci_host_bridge *bridge);
+
int pci_host_common_probe(struct platform_device *pdev);
int pci_host_common_init(struct platform_device *pdev,
struct pci_host_bridge *bridge,
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index bccc7a4bdd79..65a111361072 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -671,6 +671,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
{
INIT_LIST_HEAD(&bridge->windows);
INIT_LIST_HEAD(&bridge->dma_ranges);
+ INIT_LIST_HEAD(&bridge->ports);
/*
* We assume we can manage these PCIe features. Some systems may
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 8861eeb4381d..ac343e8f140c 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -642,6 +642,7 @@ struct pci_host_bridge {
int domain_nr;
struct list_head windows; /* resource_entry */
struct list_head dma_ranges; /* dma ranges resource list */
+ struct list_head ports; /* Root Port list (pci_host_port) */
#ifdef CONFIG_PCI_IDE
u16 nr_ide_streams; /* Max streams possibly active in @ide_stream_ida */
struct ida ide_stream_ida;
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V8 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties
2026-03-13 2:08 ` [PATCH V8 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties Sherry Sun
@ 2026-03-16 5:40 ` Manivannan Sadhasivam
2026-03-17 8:01 ` Sherry Sun
0 siblings, 1 reply; 27+ messages in thread
From: Manivannan Sadhasivam @ 2026-03-16 5:40 UTC (permalink / raw)
To: Sherry Sun
Cc: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
On Fri, Mar 13, 2026 at 10:08:12AM +0800, Sherry Sun wrote:
> Introduce generic helper functions to parse Root Port device tree nodes
> and extract common properties like reset GPIOs. This allows multiple
> PCI host controller drivers to share the same parsing logic.
>
> Define struct pci_host_port to hold common Root Port properties
> (currently only reset GPIO descriptor) and add
> pci_host_common_parse_ports() to parse Root Port nodes from device tree.
>
> Also add the 'ports' list to struct pci_host_bridge for better maintain
> parsed Root Port information.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> drivers/pci/controller/pci-host-common.c | 78 ++++++++++++++++++++++++
> drivers/pci/controller/pci-host-common.h | 15 +++++
> drivers/pci/probe.c | 1 +
> include/linux/pci.h | 1 +
> 4 files changed, 95 insertions(+)
>
> diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c
> index d6258c1cffe5..2f012cf80463 100644
> --- a/drivers/pci/controller/pci-host-common.c
> +++ b/drivers/pci/controller/pci-host-common.c
> @@ -9,6 +9,7 @@
>
> #include <linux/kernel.h>
> #include <linux/module.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> #include <linux/of_pci.h>
> @@ -17,6 +18,83 @@
>
> #include "pci-host-common.h"
>
> +/**
> + * pci_host_common_delete_ports - Cleanup function for port list
> + * @data: Pointer to the port list head
> + */
> +static void pci_host_common_delete_ports(void *data)
> +{
> + struct list_head *ports = data;
> + struct pci_host_port *port, *tmp;
> +
> + list_for_each_entry_safe(port, tmp, ports, list)
> + list_del(&port->list);
> +}
> +
> +/**
> + * pci_host_common_parse_port - Parse a single Root Port node
> + * @dev: Device pointer
> + * @bridge: PCI host bridge
> + * @node: Device tree node of the Root Port
> + *
> + * Returns: 0 on success, negative error code on failure
> + */
> +static int pci_host_common_parse_port(struct device *dev,
> + struct pci_host_bridge *bridge,
> + struct device_node *node)
> +{
> + struct pci_host_port *port;
> + struct gpio_desc *reset;
> +
> + reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> + "reset", GPIOD_ASIS, "PERST#");
> + if (IS_ERR(reset))
> + return PTR_ERR(reset);
> +
> + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> + if (!port)
> + return -ENOMEM;
> +
> + port->reset = reset;
> + INIT_LIST_HEAD(&port->list);
> + list_add_tail(&port->list, &bridge->ports);
> +
> + return 0;
> +}
> +
> +/**
> + * pci_host_common_parse_ports - Parse Root Port nodes from device tree
> + * @dev: Device pointer
> + * @bridge: PCI host bridge
> + *
> + * This function iterates through child nodes of the host bridge and parses
> + * Root Port properties (currently only reset GPIO).
> + *
> + * Returns: 0 on success, -ENOENT if no ports found, other negative error codes
> + * on failure
> + */
> +int pci_host_common_parse_ports(struct device *dev, struct pci_host_bridge *bridge)
> +{
> + int ret = -ENOENT;
> + int err;
> +
> + for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> + if (!of_node_is_type(of_port, "pci"))
> + continue;
> + ret = pci_host_common_parse_port(dev, bridge, of_port);
> + if (ret)
> + return ret;
> + }
> +
I think you should just do:
if (ret)
return ret;
and get rid of 'err'.
> + err = devm_add_action_or_reset(dev, pci_host_common_delete_ports,
> + &bridge->ports);
> + if (err)
> + return err;
> +
> + return ret;
return 0;
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [PATCH V8 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties
2026-03-16 5:40 ` Manivannan Sadhasivam
@ 2026-03-17 8:01 ` Sherry Sun
2026-03-17 9:51 ` Manivannan Sadhasivam
0 siblings, 1 reply; 27+ messages in thread
From: Sherry Sun @ 2026-03-17 8:01 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Hongxing Zhu, l.stach, Frank Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
> On Fri, Mar 13, 2026 at 10:08:12AM +0800, Sherry Sun wrote:
> > Introduce generic helper functions to parse Root Port device tree
> > nodes and extract common properties like reset GPIOs. This allows
> > multiple PCI host controller drivers to share the same parsing logic.
> >
> > Define struct pci_host_port to hold common Root Port properties
> > (currently only reset GPIO descriptor) and add
> > pci_host_common_parse_ports() to parse Root Port nodes from device
> tree.
> >
> > Also add the 'ports' list to struct pci_host_bridge for better
> > maintain parsed Root Port information.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > drivers/pci/controller/pci-host-common.c | 78
> > ++++++++++++++++++++++++ drivers/pci/controller/pci-host-common.h |
> 15 +++++
> > drivers/pci/probe.c | 1 +
> > include/linux/pci.h | 1 +
> > 4 files changed, 95 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pci-host-common.c
> > b/drivers/pci/controller/pci-host-common.c
> > index d6258c1cffe5..2f012cf80463 100644
> > --- a/drivers/pci/controller/pci-host-common.c
> > +++ b/drivers/pci/controller/pci-host-common.c
> > @@ -9,6 +9,7 @@
> >
> > #include <linux/kernel.h>
> > #include <linux/module.h>
> > +#include <linux/gpio/consumer.h>
> > #include <linux/of.h>
> > #include <linux/of_address.h>
> > #include <linux/of_pci.h>
> > @@ -17,6 +18,83 @@
> >
> > #include "pci-host-common.h"
> >
> > +/**
> > + * pci_host_common_delete_ports - Cleanup function for port list
> > + * @data: Pointer to the port list head */ static void
> > +pci_host_common_delete_ports(void *data) {
> > + struct list_head *ports = data;
> > + struct pci_host_port *port, *tmp;
> > +
> > + list_for_each_entry_safe(port, tmp, ports, list)
> > + list_del(&port->list);
> > +}
> > +
> > +/**
> > + * pci_host_common_parse_port - Parse a single Root Port node
> > + * @dev: Device pointer
> > + * @bridge: PCI host bridge
> > + * @node: Device tree node of the Root Port
> > + *
> > + * Returns: 0 on success, negative error code on failure */ static
> > +int pci_host_common_parse_port(struct device *dev,
> > + struct pci_host_bridge *bridge,
> > + struct device_node *node)
> > +{
> > + struct pci_host_port *port;
> > + struct gpio_desc *reset;
> > +
> > + reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> > + "reset", GPIOD_ASIS, "PERST#");
> > + if (IS_ERR(reset))
> > + return PTR_ERR(reset);
> > +
> > + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > + if (!port)
> > + return -ENOMEM;
> > +
> > + port->reset = reset;
> > + INIT_LIST_HEAD(&port->list);
> > + list_add_tail(&port->list, &bridge->ports);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * pci_host_common_parse_ports - Parse Root Port nodes from device
> > +tree
> > + * @dev: Device pointer
> > + * @bridge: PCI host bridge
> > + *
> > + * This function iterates through child nodes of the host bridge and
> > +parses
> > + * Root Port properties (currently only reset GPIO).
> > + *
> > + * Returns: 0 on success, -ENOENT if no ports found, other negative
> > +error codes
> > + * on failure
> > + */
> > +int pci_host_common_parse_ports(struct device *dev, struct
> > +pci_host_bridge *bridge) {
> > + int ret = -ENOENT;
> > + int err;
> > +
> > + for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> > + if (!of_node_is_type(of_port, "pci"))
> > + continue;
> > + ret = pci_host_common_parse_port(dev, bridge, of_port);
> > + if (ret)
> > + return ret;
> > + }
> > +
>
> I think you should just do:
>
> if (ret)
> return ret;
>
> and get rid of 'err'.
Hi Mani, do you mean the following method?
int pci_host_common_parse_ports(struct device *dev, struct pci_host_bridge *bridge)
{
int ret = -ENOENT;
for_each_available_child_of_node_scoped(dev->of_node, of_port) {
if (!of_node_is_type(of_port, "pci"))
continue;
ret = pci_host_common_parse_port(dev, bridge, of_port);
if (ret)
return ret;
}
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, pci_host_common_delete_ports,
&bridge->ports);
if (ret)
return ret;
return 0;
}
But the error path looks a bit redundant to me, how about check if (ret == 0) before
devm_add_action_or_reset() directly?
int pci_host_common_parse_ports(struct device *dev, struct pci_host_bridge *bridge)
{
int ret = -ENOENT;
for_each_available_child_of_node_scoped(dev->of_node, of_port) {
if (!of_node_is_type(of_port, "pci"))
continue;
ret = pci_host_common_parse_port(dev, bridge, of_port);
if (ret)
return ret;
}
if (ret == 0)
ret = devm_add_action_or_reset(dev, pci_host_common_delete_ports,
&bridge->ports);
return ret;
}
Best Regards
Sherry
>
> > + err = devm_add_action_or_reset(dev,
> pci_host_common_delete_ports,
> > + &bridge->ports);
> > + if (err)
> > + return err;
> > +
> > + return ret;
>
> return 0;
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V8 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties
2026-03-17 8:01 ` Sherry Sun
@ 2026-03-17 9:51 ` Manivannan Sadhasivam
2026-03-17 10:35 ` Sherry Sun
0 siblings, 1 reply; 27+ messages in thread
From: Manivannan Sadhasivam @ 2026-03-17 9:51 UTC (permalink / raw)
To: Sherry Sun
Cc: Hongxing Zhu, l.stach, Frank Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
On Tue, Mar 17, 2026 at 08:01:28AM +0000, Sherry Sun wrote:
>
> > On Fri, Mar 13, 2026 at 10:08:12AM +0800, Sherry Sun wrote:
> > > Introduce generic helper functions to parse Root Port device tree
> > > nodes and extract common properties like reset GPIOs. This allows
> > > multiple PCI host controller drivers to share the same parsing logic.
> > >
> > > Define struct pci_host_port to hold common Root Port properties
> > > (currently only reset GPIO descriptor) and add
> > > pci_host_common_parse_ports() to parse Root Port nodes from device
> > tree.
> > >
> > > Also add the 'ports' list to struct pci_host_bridge for better
> > > maintain parsed Root Port information.
> > >
> > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > ---
> > > drivers/pci/controller/pci-host-common.c | 78
> > > ++++++++++++++++++++++++ drivers/pci/controller/pci-host-common.h |
> > 15 +++++
> > > drivers/pci/probe.c | 1 +
> > > include/linux/pci.h | 1 +
> > > 4 files changed, 95 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/pci-host-common.c
> > > b/drivers/pci/controller/pci-host-common.c
> > > index d6258c1cffe5..2f012cf80463 100644
> > > --- a/drivers/pci/controller/pci-host-common.c
> > > +++ b/drivers/pci/controller/pci-host-common.c
> > > @@ -9,6 +9,7 @@
> > >
> > > #include <linux/kernel.h>
> > > #include <linux/module.h>
> > > +#include <linux/gpio/consumer.h>
> > > #include <linux/of.h>
> > > #include <linux/of_address.h>
> > > #include <linux/of_pci.h>
> > > @@ -17,6 +18,83 @@
> > >
> > > #include "pci-host-common.h"
> > >
> > > +/**
> > > + * pci_host_common_delete_ports - Cleanup function for port list
> > > + * @data: Pointer to the port list head */ static void
> > > +pci_host_common_delete_ports(void *data) {
> > > + struct list_head *ports = data;
> > > + struct pci_host_port *port, *tmp;
> > > +
> > > + list_for_each_entry_safe(port, tmp, ports, list)
> > > + list_del(&port->list);
> > > +}
> > > +
> > > +/**
> > > + * pci_host_common_parse_port - Parse a single Root Port node
> > > + * @dev: Device pointer
> > > + * @bridge: PCI host bridge
> > > + * @node: Device tree node of the Root Port
> > > + *
> > > + * Returns: 0 on success, negative error code on failure */ static
> > > +int pci_host_common_parse_port(struct device *dev,
> > > + struct pci_host_bridge *bridge,
> > > + struct device_node *node)
> > > +{
> > > + struct pci_host_port *port;
> > > + struct gpio_desc *reset;
> > > +
> > > + reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> > > + "reset", GPIOD_ASIS, "PERST#");
> > > + if (IS_ERR(reset))
> > > + return PTR_ERR(reset);
> > > +
> > > + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > > + if (!port)
> > > + return -ENOMEM;
> > > +
> > > + port->reset = reset;
> > > + INIT_LIST_HEAD(&port->list);
> > > + list_add_tail(&port->list, &bridge->ports);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +/**
> > > + * pci_host_common_parse_ports - Parse Root Port nodes from device
> > > +tree
> > > + * @dev: Device pointer
> > > + * @bridge: PCI host bridge
> > > + *
> > > + * This function iterates through child nodes of the host bridge and
> > > +parses
> > > + * Root Port properties (currently only reset GPIO).
> > > + *
> > > + * Returns: 0 on success, -ENOENT if no ports found, other negative
> > > +error codes
> > > + * on failure
> > > + */
> > > +int pci_host_common_parse_ports(struct device *dev, struct
> > > +pci_host_bridge *bridge) {
> > > + int ret = -ENOENT;
> > > + int err;
> > > +
> > > + for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> > > + if (!of_node_is_type(of_port, "pci"))
> > > + continue;
> > > + ret = pci_host_common_parse_port(dev, bridge, of_port);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> >
> > I think you should just do:
> >
> > if (ret)
> > return ret;
> >
> > and get rid of 'err'.
>
> Hi Mani, do you mean the following method?
>
> int pci_host_common_parse_ports(struct device *dev, struct pci_host_bridge *bridge)
> {
> int ret = -ENOENT;
>
> for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> if (!of_node_is_type(of_port, "pci"))
> continue;
> ret = pci_host_common_parse_port(dev, bridge, of_port);
> if (ret)
> return ret;
> }
>
> if (ret)
> return ret;
>
> ret = devm_add_action_or_reset(dev, pci_host_common_delete_ports,
> &bridge->ports);
Here, you can do 'return devm_add_action_or_reset()'
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [PATCH V8 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties
2026-03-17 9:51 ` Manivannan Sadhasivam
@ 2026-03-17 10:35 ` Sherry Sun
0 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-17 10:35 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Hongxing Zhu, l.stach, Frank Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
> On Tue, Mar 17, 2026 at 08:01:28AM +0000, Sherry Sun wrote:
> >
> > > On Fri, Mar 13, 2026 at 10:08:12AM +0800, Sherry Sun wrote:
> > > > Introduce generic helper functions to parse Root Port device tree
> > > > nodes and extract common properties like reset GPIOs. This allows
> > > > multiple PCI host controller drivers to share the same parsing logic.
> > > >
> > > > Define struct pci_host_port to hold common Root Port properties
> > > > (currently only reset GPIO descriptor) and add
> > > > pci_host_common_parse_ports() to parse Root Port nodes from device
> > > tree.
> > > >
> > > > Also add the 'ports' list to struct pci_host_bridge for better
> > > > maintain parsed Root Port information.
> > > >
> > > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > > ---
> > > > drivers/pci/controller/pci-host-common.c | 78
> > > > ++++++++++++++++++++++++ drivers/pci/controller/pci-host-common.h
> > > > ++++++++++++++++++++++++ |
> > > 15 +++++
> > > > drivers/pci/probe.c | 1 +
> > > > include/linux/pci.h | 1 +
> > > > 4 files changed, 95 insertions(+)
> > > >
> > > > diff --git a/drivers/pci/controller/pci-host-common.c
> > > > b/drivers/pci/controller/pci-host-common.c
> > > > index d6258c1cffe5..2f012cf80463 100644
> > > > --- a/drivers/pci/controller/pci-host-common.c
> > > > +++ b/drivers/pci/controller/pci-host-common.c
> > > > @@ -9,6 +9,7 @@
> > > >
> > > > #include <linux/kernel.h>
> > > > #include <linux/module.h>
> > > > +#include <linux/gpio/consumer.h>
> > > > #include <linux/of.h>
> > > > #include <linux/of_address.h>
> > > > #include <linux/of_pci.h>
> > > > @@ -17,6 +18,83 @@
> > > >
> > > > #include "pci-host-common.h"
> > > >
> > > > +/**
> > > > + * pci_host_common_delete_ports - Cleanup function for port list
> > > > + * @data: Pointer to the port list head */ static void
> > > > +pci_host_common_delete_ports(void *data) {
> > > > + struct list_head *ports = data;
> > > > + struct pci_host_port *port, *tmp;
> > > > +
> > > > + list_for_each_entry_safe(port, tmp, ports, list)
> > > > + list_del(&port->list);
> > > > +}
> > > > +
> > > > +/**
> > > > + * pci_host_common_parse_port - Parse a single Root Port node
> > > > + * @dev: Device pointer
> > > > + * @bridge: PCI host bridge
> > > > + * @node: Device tree node of the Root Port
> > > > + *
> > > > + * Returns: 0 on success, negative error code on failure */
> > > > +static int pci_host_common_parse_port(struct device *dev,
> > > > + struct pci_host_bridge *bridge,
> > > > + struct device_node *node) {
> > > > + struct pci_host_port *port;
> > > > + struct gpio_desc *reset;
> > > > +
> > > > + reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> > > > + "reset", GPIOD_ASIS, "PERST#");
> > > > + if (IS_ERR(reset))
> > > > + return PTR_ERR(reset);
> > > > +
> > > > + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > > > + if (!port)
> > > > + return -ENOMEM;
> > > > +
> > > > + port->reset = reset;
> > > > + INIT_LIST_HEAD(&port->list);
> > > > + list_add_tail(&port->list, &bridge->ports);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +/**
> > > > + * pci_host_common_parse_ports - Parse Root Port nodes from
> > > > +device tree
> > > > + * @dev: Device pointer
> > > > + * @bridge: PCI host bridge
> > > > + *
> > > > + * This function iterates through child nodes of the host bridge
> > > > +and parses
> > > > + * Root Port properties (currently only reset GPIO).
> > > > + *
> > > > + * Returns: 0 on success, -ENOENT if no ports found, other
> > > > +negative error codes
> > > > + * on failure
> > > > + */
> > > > +int pci_host_common_parse_ports(struct device *dev, struct
> > > > +pci_host_bridge *bridge) {
> > > > + int ret = -ENOENT;
> > > > + int err;
> > > > +
> > > > + for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> > > > + if (!of_node_is_type(of_port, "pci"))
> > > > + continue;
> > > > + ret = pci_host_common_parse_port(dev, bridge, of_port);
> > > > + if (ret)
> > > > + return ret;
> > > > + }
> > > > +
> > >
> > > I think you should just do:
> > >
> > > if (ret)
> > > return ret;
> > >
> > > and get rid of 'err'.
> >
> > Hi Mani, do you mean the following method?
> >
> > int pci_host_common_parse_ports(struct device *dev, struct
> > pci_host_bridge *bridge) {
> > int ret = -ENOENT;
> >
> > for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> > if (!of_node_is_type(of_port, "pci"))
> > continue;
> > ret = pci_host_common_parse_port(dev, bridge, of_port);
> > if (ret)
> > return ret;
> > }
> >
> > if (ret)
> > return ret;
> >
> > ret = devm_add_action_or_reset(dev, pci_host_common_delete_ports,
> > &bridge->ports);
>
> Here, you can do 'return devm_add_action_or_reset()'
Hi Mani, this sounds good to me, will fix this in V9, thanks!
Best Regards
Sherry
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in dw_pcie_host_init()
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
2026-03-13 2:08 ` [PATCH V8 01/13] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node Sherry Sun
2026-03-13 2:08 ` [PATCH V8 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-16 5:56 ` Manivannan Sadhasivam
2026-03-13 2:08 ` [PATCH V8 04/13] PCI: imx6: Assert PERST# before enabling regulators Sherry Sun
` (9 subsequent siblings)
12 siblings, 1 reply; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Add support for parsing Root Port child nodes in dw_pcie_host_init()
using pci_host_common_parse_ports(). This allows DWC-based drivers to
specify Root Port properties (like reset GPIOs) in individual Root Port
nodes rather than in the host bridge node.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index a74339982c24..9608f9fcd1b3 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include "../../pci.h"
+#include "../pci-host-common.h"
#include "pcie-designware.h"
static struct pci_ops dw_pcie_ops;
@@ -581,6 +582,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
pp->bridge = bridge;
+ /* Parse Root Port nodes if present */
+ ret = pci_host_common_parse_ports(dev, bridge);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "Failed to parse Root Port nodes: %d\n", ret);
+ return ret;
+ }
+
ret = dw_pcie_host_get_resources(pp);
if (ret)
return ret;
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in dw_pcie_host_init()
2026-03-13 2:08 ` [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in dw_pcie_host_init() Sherry Sun
@ 2026-03-16 5:56 ` Manivannan Sadhasivam
2026-03-17 9:04 ` Sherry Sun
0 siblings, 1 reply; 27+ messages in thread
From: Manivannan Sadhasivam @ 2026-03-16 5:56 UTC (permalink / raw)
To: Sherry Sun
Cc: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
On Fri, Mar 13, 2026 at 10:08:13AM +0800, Sherry Sun wrote:
> Add support for parsing Root Port child nodes in dw_pcie_host_init()
> using pci_host_common_parse_ports(). This allows DWC-based drivers to
> specify Root Port properties (like reset GPIOs) in individual Root Port
> nodes rather than in the host bridge node.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index a74339982c24..9608f9fcd1b3 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -20,6 +20,7 @@
> #include <linux/platform_device.h>
>
> #include "../../pci.h"
> +#include "../pci-host-common.h"
> #include "pcie-designware.h"
>
> static struct pci_ops dw_pcie_ops;
> @@ -581,6 +582,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>
> pp->bridge = bridge;
>
> + /* Parse Root Port nodes if present */
> + ret = pci_host_common_parse_ports(dev, bridge);
> + if (ret && ret != -ENOENT) {
Is there an incentive in the -ENOENT error code? Should the API just return 0 if
no ports are found?
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in dw_pcie_host_init()
2026-03-16 5:56 ` Manivannan Sadhasivam
@ 2026-03-17 9:04 ` Sherry Sun
2026-03-17 9:58 ` Manivannan Sadhasivam
0 siblings, 1 reply; 27+ messages in thread
From: Sherry Sun @ 2026-03-17 9:04 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Hongxing Zhu, l.stach, Frank Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
> Subject: Re: [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in
> dw_pcie_host_init()
>
> On Fri, Mar 13, 2026 at 10:08:13AM +0800, Sherry Sun wrote:
> > Add support for parsing Root Port child nodes in dw_pcie_host_init()
> > using pci_host_common_parse_ports(). This allows DWC-based drivers to
> > specify Root Port properties (like reset GPIOs) in individual Root
> > Port nodes rather than in the host bridge node.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
> > b/drivers/pci/controller/dwc/pcie-designware-host.c
> > index a74339982c24..9608f9fcd1b3 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > @@ -20,6 +20,7 @@
> > #include <linux/platform_device.h>
> >
> > #include "../../pci.h"
> > +#include "../pci-host-common.h"
> > #include "pcie-designware.h"
> >
> > static struct pci_ops dw_pcie_ops;
> > @@ -581,6 +582,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> >
> > pp->bridge = bridge;
> >
> > + /* Parse Root Port nodes if present */
> > + ret = pci_host_common_parse_ports(dev, bridge);
> > + if (ret && ret != -ENOENT) {
>
> Is there an incentive in the -ENOENT error code? Should the API just return 0
> if no ports are found?
>
Hi Mani,
Since devm_fwnode_gpiod_get() is called within pci_host_common_parse_ports(),
devm_fwnode_gpiod_get() will return -ENOENT if no GPIO found. That means we
need to check and handle the -ENOENT error anyway, we can either handle it internally
in pci_host_common_parse_ports() or in the upper caller.
If we hide -ENOENT inside pci_host_common_parse_ports() and always return 0, we
lose this distinction, the caller can no longer tell the difference between "not found" and
"found and parsed successfully". This might be useful that different callers might want to
handle differently.
The current pattern is also consistent with some other optional resource APIs in the
kernel (e.g., devm_regulator_get_optional()), where -ENOENT is returned and the caller
decides how to handle it.
Best Regards
Sherry
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in dw_pcie_host_init()
2026-03-17 9:04 ` Sherry Sun
@ 2026-03-17 9:58 ` Manivannan Sadhasivam
0 siblings, 0 replies; 27+ messages in thread
From: Manivannan Sadhasivam @ 2026-03-17 9:58 UTC (permalink / raw)
To: Sherry Sun
Cc: Hongxing Zhu, l.stach, Frank Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
On Tue, Mar 17, 2026 at 09:04:51AM +0000, Sherry Sun wrote:
> > Subject: Re: [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in
> > dw_pcie_host_init()
> >
> > On Fri, Mar 13, 2026 at 10:08:13AM +0800, Sherry Sun wrote:
> > > Add support for parsing Root Port child nodes in dw_pcie_host_init()
> > > using pci_host_common_parse_ports(). This allows DWC-based drivers to
> > > specify Root Port properties (like reset GPIOs) in individual Root
> > > Port nodes rather than in the host bridge node.
> > >
> > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > ---
> > > drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > index a74339982c24..9608f9fcd1b3 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > @@ -20,6 +20,7 @@
> > > #include <linux/platform_device.h>
> > >
> > > #include "../../pci.h"
> > > +#include "../pci-host-common.h"
> > > #include "pcie-designware.h"
> > >
> > > static struct pci_ops dw_pcie_ops;
> > > @@ -581,6 +582,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> > >
> > > pp->bridge = bridge;
> > >
> > > + /* Parse Root Port nodes if present */
> > > + ret = pci_host_common_parse_ports(dev, bridge);
> > > + if (ret && ret != -ENOENT) {
> >
> > Is there an incentive in the -ENOENT error code? Should the API just return 0
> > if no ports are found?
> >
>
> Hi Mani,
>
> Since devm_fwnode_gpiod_get() is called within pci_host_common_parse_ports(),
> devm_fwnode_gpiod_get() will return -ENOENT if no GPIO found. That means we
> need to check and handle the -ENOENT error anyway, we can either handle it internally
> in pci_host_common_parse_ports() or in the upper caller.
>
> If we hide -ENOENT inside pci_host_common_parse_ports() and always return 0, we
> lose this distinction, the caller can no longer tell the difference between "not found" and
> "found and parsed successfully". This might be useful that different callers might want to
> handle differently.
>
> The current pattern is also consistent with some other optional resource APIs in the
> kernel (e.g., devm_regulator_get_optional()), where -ENOENT is returned and the caller
> decides how to handle it.
>
Sure. But since the current callers are not making use of it, I thought of just
returning 0. It fine with me to leave it as is.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V8 04/13] PCI: imx6: Assert PERST# before enabling regulators
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (2 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 03/13] PCI: dwc: Parse Root Port nodes in dw_pcie_host_init() Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 2:08 ` [PATCH V8 05/13] PCI: imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (8 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
According to the PCIe initialization requirements, PERST# signal should
be asserted before applying power to the PCIe device, and deasserted
after power and reference clock are stable.
Currently, the driver enables the vpcie3v3aux regulator in
imx_pcie_probe() before PERST# is asserted in imx_pcie_host_init(),
which violates the PCIe power sequencing requirements. However, there
is no issue so far because PERST# is requested as GPIOD_OUT_HIGH in
imx_pcie_probe(), which guarantees that PERST# is asserted before
enabling the vpcie3v3aux regulator.
This is prepare for the upcoming changes that will parse the reset
property using the new Root Port binding, which will use GPIOD_ASIS
when requesting the reset GPIO. With GPIOD_ASIS, the GPIO state is not
guaranteed, so explicit sequencing is required.
Fix the power sequencing by:
1. Moving vpcie3v3aux regulator enable from probe to
imx_pcie_host_init(), where it can be properly sequenced with PERST#.
2. Moving imx_pcie_assert_perst() before regulator and clock enable to
ensure correct ordering.
The vpcie3v3aux regulator is kept enabled for the entire PCIe controller
lifecycle and automatically disabled on device removal via devm cleanup.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 49 +++++++++++++++++++++------
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index d80d3be28ee5..83beca5a1fc2 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -166,6 +166,8 @@ struct imx_pcie {
u32 tx_swing_full;
u32 tx_swing_low;
struct regulator *vpcie;
+ struct regulator *vpcie_aux;
+ bool vpcie_aux_enabled;
struct regulator *vph;
void __iomem *phy_base;
@@ -1220,6 +1222,13 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,
imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));
}
+static void imx_pcie_vpcie_aux_disable(void *data)
+{
+ struct regulator *vpcie_aux = data;
+
+ regulator_disable(vpcie_aux);
+}
+
static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)
{
if (assert) {
@@ -1240,6 +1249,24 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
struct imx_pcie *imx_pcie = to_imx_pcie(pci);
int ret;
+ imx_pcie_assert_perst(imx_pcie, true);
+
+ /* Keep 3.3Vaux supply enabled for the entire PCIe controller lifecycle */
+ if (imx_pcie->vpcie_aux && !imx_pcie->vpcie_aux_enabled) {
+ ret = regulator_enable(imx_pcie->vpcie_aux);
+ if (ret) {
+ dev_err(dev, "failed to enable vpcie_aux regulator: %d\n",
+ ret);
+ return ret;
+ }
+ imx_pcie->vpcie_aux_enabled = true;
+
+ ret = devm_add_action_or_reset(dev, imx_pcie_vpcie_aux_disable,
+ imx_pcie->vpcie_aux);
+ if (ret)
+ return ret;
+ }
+
if (imx_pcie->vpcie) {
ret = regulator_enable(imx_pcie->vpcie);
if (ret) {
@@ -1249,25 +1276,24 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
}
}
+ ret = imx_pcie_clk_enable(imx_pcie);
+ if (ret) {
+ dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
+ goto err_reg_disable;
+ }
+
if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) {
pp->bridge->enable_device = imx_pcie_enable_device;
pp->bridge->disable_device = imx_pcie_disable_device;
}
imx_pcie_assert_core_reset(imx_pcie);
- imx_pcie_assert_perst(imx_pcie, true);
if (imx_pcie->drvdata->init_phy)
imx_pcie->drvdata->init_phy(imx_pcie);
imx_pcie_configure_type(imx_pcie);
- ret = imx_pcie_clk_enable(imx_pcie);
- if (ret) {
- dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
- goto err_reg_disable;
- }
-
if (imx_pcie->phy) {
ret = phy_init(imx_pcie->phy);
if (ret) {
@@ -1790,9 +1816,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
imx_pcie->supports_clkreq = of_property_read_bool(node, "supports-clkreq");
- ret = devm_regulator_get_enable_optional(&pdev->dev, "vpcie3v3aux");
- if (ret < 0 && ret != -ENODEV)
- return dev_err_probe(dev, ret, "failed to enable Vaux supply\n");
+ imx_pcie->vpcie_aux = devm_regulator_get_optional(&pdev->dev, "vpcie3v3aux");
+ if (IS_ERR(imx_pcie->vpcie_aux)) {
+ if (PTR_ERR(imx_pcie->vpcie_aux) != -ENODEV)
+ return PTR_ERR(imx_pcie->vpcie_aux);
+ imx_pcie->vpcie_aux = NULL;
+ }
imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
if (IS_ERR(imx_pcie->vpcie)) {
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V8 05/13] PCI: imx6: Add support for parsing the reset property in new Root Port binding
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (3 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 04/13] PCI: imx6: Assert PERST# before enabling regulators Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-16 6:04 ` Manivannan Sadhasivam
2026-03-13 2:08 ` [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property Sherry Sun
` (7 subsequent siblings)
12 siblings, 1 reply; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
The current DT binding for pci-imx6 specifies the 'reset-gpios' property
in the host bridge node. However, the PERST# signal logically belongs to
individual Root Ports rather than the host bridge itself. This becomes
important when supporting PCIe KeyE connector and PCI power control
framework for pci-imx6 driver, which requires properties to be specified
in Root Port nodes.
With the common Root Port parsing now handled in dw_pcie_host_init(),
update the reset GPIO handling to use the parsed port list from
bridge->ports. To maintain DT backwards compatibility, fallback to the
legacy method of parsing the host bridge node if the reset property is
not present in the Root Port node (indicated by an empty ports list).
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 74 +++++++++++++++++++++------
1 file changed, 59 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 83beca5a1fc2..cb18e1579788 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -34,6 +34,7 @@
#include <linux/pm_runtime.h>
#include "../../pci.h"
+#include "../pci-host-common.h"
#include "pcie-designware.h"
#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
@@ -150,7 +151,6 @@ struct imx_lut_data {
struct imx_pcie {
struct dw_pcie *pci;
- struct gpio_desc *reset_gpiod;
struct clk_bulk_data *clks;
int num_clks;
bool supports_clkreq;
@@ -1222,6 +1222,44 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,
imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));
}
+static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)
+{
+ struct device *dev = pcie->pci->dev;
+ struct pci_host_bridge *bridge = pcie->pci->pp.bridge;
+ struct pci_host_port *port;
+ struct gpio_desc *reset;
+
+ if (!bridge) {
+ dev_err(dev, "Bridge not allocated yet\n");
+ return -EINVAL;
+ }
+
+ /*
+ * For DT backward compatibility: if no Root Port nodes were parsed
+ * (indicated by empty ports list), parse reset-gpios from the host
+ * bridge node.
+ */
+ if (!list_empty(&bridge->ports))
+ return 0;
+
+ reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
+ if (IS_ERR(reset))
+ return PTR_ERR(reset);
+
+ if (!reset)
+ return 0;
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ port->reset = reset;
+ INIT_LIST_HEAD(&port->list);
+ list_add_tail(&port->list, &bridge->ports);
+
+ return 0;
+}
+
static void imx_pcie_vpcie_aux_disable(void *data)
{
struct regulator *vpcie_aux = data;
@@ -1231,13 +1269,22 @@ static void imx_pcie_vpcie_aux_disable(void *data)
static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)
{
- if (assert) {
- gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);
- } else {
- if (imx_pcie->reset_gpiod) {
- msleep(PCIE_T_PVPERL_MS);
- gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);
- msleep(PCIE_RESET_CONFIG_WAIT_MS);
+ struct dw_pcie *pci = imx_pcie->pci;
+ struct pci_host_bridge *bridge = pci->pp.bridge;
+ struct pci_host_port *port;
+
+ if (!bridge)
+ return;
+
+ list_for_each_entry(port, &bridge->ports, list) {
+ if (assert) {
+ gpiod_set_value_cansleep(port->reset, 1);
+ } else {
+ if (port->reset) {
+ msleep(PCIE_T_PVPERL_MS);
+ gpiod_set_value_cansleep(port->reset, 0);
+ msleep(PCIE_RESET_CONFIG_WAIT_MS);
+ }
}
}
}
@@ -1249,6 +1296,10 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
struct imx_pcie *imx_pcie = to_imx_pcie(pci);
int ret;
+ ret = imx_pcie_parse_legacy_binding(imx_pcie);
+ if (ret)
+ return ret;
+
imx_pcie_assert_perst(imx_pcie, true);
/* Keep 3.3Vaux supply enabled for the entire PCIe controller lifecycle */
@@ -1712,13 +1763,6 @@ static int imx_pcie_probe(struct platform_device *pdev)
return PTR_ERR(imx_pcie->phy_base);
}
- /* Fetch GPIOs */
- imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
- if (IS_ERR(imx_pcie->reset_gpiod))
- return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),
- "unable to get reset gpio\n");
- gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
-
/* Fetch clocks */
imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);
if (imx_pcie->num_clks < 0)
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V8 05/13] PCI: imx6: Add support for parsing the reset property in new Root Port binding
2026-03-13 2:08 ` [PATCH V8 05/13] PCI: imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
@ 2026-03-16 6:04 ` Manivannan Sadhasivam
2026-03-17 9:09 ` Sherry Sun
0 siblings, 1 reply; 27+ messages in thread
From: Manivannan Sadhasivam @ 2026-03-16 6:04 UTC (permalink / raw)
To: Sherry Sun
Cc: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
On Fri, Mar 13, 2026 at 10:08:15AM +0800, Sherry Sun wrote:
> The current DT binding for pci-imx6 specifies the 'reset-gpios' property
> in the host bridge node. However, the PERST# signal logically belongs to
> individual Root Ports rather than the host bridge itself. This becomes
> important when supporting PCIe KeyE connector and PCI power control
> framework for pci-imx6 driver, which requires properties to be specified
> in Root Port nodes.
>
> With the common Root Port parsing now handled in dw_pcie_host_init(),
> update the reset GPIO handling to use the parsed port list from
> bridge->ports. To maintain DT backwards compatibility, fallback to the
> legacy method of parsing the host bridge node if the reset property is
> not present in the Root Port node (indicated by an empty ports list).
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 74 +++++++++++++++++++++------
> 1 file changed, 59 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 83beca5a1fc2..cb18e1579788 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -34,6 +34,7 @@
> #include <linux/pm_runtime.h>
>
> #include "../../pci.h"
> +#include "../pci-host-common.h"
> #include "pcie-designware.h"
>
> #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
> @@ -150,7 +151,6 @@ struct imx_lut_data {
>
> struct imx_pcie {
> struct dw_pcie *pci;
> - struct gpio_desc *reset_gpiod;
> struct clk_bulk_data *clks;
> int num_clks;
> bool supports_clkreq;
> @@ -1222,6 +1222,44 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,
> imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));
> }
>
> +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)
> +{
> + struct device *dev = pcie->pci->dev;
> + struct pci_host_bridge *bridge = pcie->pci->pp.bridge;
> + struct pci_host_port *port;
> + struct gpio_desc *reset;
> +
> + if (!bridge) {
> + dev_err(dev, "Bridge not allocated yet\n");
> + return -EINVAL;
> + }
> +
> + /*
> + * For DT backward compatibility: if no Root Port nodes were parsed
> + * (indicated by empty ports list), parse reset-gpios from the host
> + * bridge node.
> + */
> + if (!list_empty(&bridge->ports))
You should move this check and the comment to imx_pcie_host_init() and call
imx_pcie_parse_legacy_binding() conditionally to make it clear that this is a
fallback.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [PATCH V8 05/13] PCI: imx6: Add support for parsing the reset property in new Root Port binding
2026-03-16 6:04 ` Manivannan Sadhasivam
@ 2026-03-17 9:09 ` Sherry Sun
0 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-17 9:09 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Hongxing Zhu, l.stach, Frank Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
> On Fri, Mar 13, 2026 at 10:08:15AM +0800, Sherry Sun wrote:
> > The current DT binding for pci-imx6 specifies the 'reset-gpios'
> > property in the host bridge node. However, the PERST# signal logically
> > belongs to individual Root Ports rather than the host bridge itself.
> > This becomes important when supporting PCIe KeyE connector and PCI
> > power control framework for pci-imx6 driver, which requires properties
> > to be specified in Root Port nodes.
> >
> > With the common Root Port parsing now handled in dw_pcie_host_init(),
> > update the reset GPIO handling to use the parsed port list from
> > bridge->ports. To maintain DT backwards compatibility, fallback to the
> > legacy method of parsing the host bridge node if the reset property is
> > not present in the Root Port node (indicated by an empty ports list).
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 74
> > +++++++++++++++++++++------
> > 1 file changed, 59 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 83beca5a1fc2..cb18e1579788 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -34,6 +34,7 @@
> > #include <linux/pm_runtime.h>
> >
> > #include "../../pci.h"
> > +#include "../pci-host-common.h"
> > #include "pcie-designware.h"
> >
> > #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
> > @@ -150,7 +151,6 @@ struct imx_lut_data {
> >
> > struct imx_pcie {
> > struct dw_pcie *pci;
> > - struct gpio_desc *reset_gpiod;
> > struct clk_bulk_data *clks;
> > int num_clks;
> > bool supports_clkreq;
> > @@ -1222,6 +1222,44 @@ static void imx_pcie_disable_device(struct
> pci_host_bridge *bridge,
> > imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); }
> >
> > +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie) {
> > + struct device *dev = pcie->pci->dev;
> > + struct pci_host_bridge *bridge = pcie->pci->pp.bridge;
> > + struct pci_host_port *port;
> > + struct gpio_desc *reset;
> > +
> > + if (!bridge) {
> > + dev_err(dev, "Bridge not allocated yet\n");
> > + return -EINVAL;
> > + }
> > +
> > + /*
> > + * For DT backward compatibility: if no Root Port nodes were parsed
> > + * (indicated by empty ports list), parse reset-gpios from the host
> > + * bridge node.
> > + */
> > + if (!list_empty(&bridge->ports))
>
> You should move this check and the comment to imx_pcie_host_init() and call
> imx_pcie_parse_legacy_binding() conditionally to make it clear that this is a
> fallback.
>
Ok, thanks for the suggestion, will do this in V9.
Best Regards
Sherry
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (4 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 05/13] PCI: imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 6:08 ` Chen-Yu Tsai
2026-03-13 2:08 ` [PATCH V8 07/13] arm: dts: imx6sx: " Sherry Sun
` (6 subsequent siblings)
12 siblings, 1 reply; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++
arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
index ba29720e3f72..fe9046c03ddd 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
@@ -754,11 +754,16 @@ lvds0_out: endpoint {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie>;
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
index 4dc2c410cf61..9438862b9927 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
@@ -302,6 +302,17 @@ pcie: pcie@1ffc000 {
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
status = "disabled";
+
+ pcie_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
aips1: bus@2000000 { /* AIPS1 */
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
index c5b220aeaefd..6b12cab7175f 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
@@ -45,10 +45,15 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
};
&pcie {
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+};
+
&sata {
status = "okay";
};
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property
2026-03-13 2:08 ` [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property Sherry Sun
@ 2026-03-13 6:08 ` Chen-Yu Tsai
2026-03-13 7:16 ` Sherry Sun
2026-03-16 5:30 ` Manivannan Sadhasivam
0 siblings, 2 replies; 27+ messages in thread
From: Chen-Yu Tsai @ 2026-03-13 6:08 UTC (permalink / raw)
To: Sherry Sun
Cc: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam,
imx, kernel, linux-pci, linux-arm-kernel, devicetree,
linux-kernel
On Fri, Mar 13, 2026 at 10:08 AM Sherry Sun <sherry.sun@nxp.com> wrote:
>
> Since describing the PCIe PERST# property under Host Bridge node is now
> deprecated, it is recommended to add it to the Root Port node, so
> creating the Root Port node and add the reset-gpios property in Root
> Port.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++
> arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++
> arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++
> 3 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> index ba29720e3f72..fe9046c03ddd 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> @@ -754,11 +754,16 @@ lvds0_out: endpoint {
> &pcie {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie>;
> + /* This property is deprecated, use reset-gpios from the Root Port node. */
> reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
I'd say just remove the old description.
You're asking for trouble by describing the same thing in two different places.
> vpcie-supply = <®_pcie>;
I would probably also take this chance to just convert to the proper PCI
slot supply, and just add pwrctrl support into your PCIe driver.
> status = "okay";
> };
>
> +&pcie_port0 {
> + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
> +};
> +
> &pwm1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pwm1>;
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> index 4dc2c410cf61..9438862b9927 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> @@ -302,6 +302,17 @@ pcie: pcie@1ffc000 {
> <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> clock-names = "pcie", "pcie_bus", "pcie_phy";
> status = "disabled";
> +
> + pcie_port0: pcie@0 {
> + compatible = "pciclass,0604";
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> };
>
> aips1: bus@2000000 { /* AIPS1 */
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> index c5b220aeaefd..6b12cab7175f 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> @@ -45,10 +45,15 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
> };
>
> &pcie {
> + /* This property is deprecated, use reset-gpios from the Root Port node. */
> reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
> status = "okay";
> };
>
> +&pcie_port0 {
> + reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>;
> +};
> +
> &sata {
> status = "okay";
> };
> --
> 2.37.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property
2026-03-13 6:08 ` Chen-Yu Tsai
@ 2026-03-13 7:16 ` Sherry Sun
2026-03-16 5:30 ` Manivannan Sadhasivam
1 sibling, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 7:16 UTC (permalink / raw)
To: wens
Cc: Hongxing Zhu, l.stach, Frank Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam,
imx, kernel, linux-pci, linux-arm-kernel, devicetree,
linux-kernel
> On Fri, Mar 13, 2026 at 10:08 AM Sherry Sun <sherry.sun@nxp.com> wrote:
> >
> > Since describing the PCIe PERST# property under Host Bridge node is
> > now deprecated, it is recommended to add it to the Root Port node, so
> > creating the Root Port node and add the reset-gpios property in Root
> > Port.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++
> > arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++
> > arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++
> > 3 files changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > index ba29720e3f72..fe9046c03ddd 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > @@ -754,11 +754,16 @@ lvds0_out: endpoint { &pcie {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_pcie>;
> > + /* This property is deprecated, use reset-gpios from the Root
> > + Port node. */
> > reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
>
> I'd say just remove the old description.
>
> You're asking for trouble by describing the same thing in two different places.
Hi Chen-Yu,
Thanks for the comments, actually this topic has been discussed in V1 and V3, the
conclusion is to add a comment here to avoid confusion, will remove the deprecated
reset-gpio property together with this comment after the pci part driver merged.
https://lore.kernel.org/linux-devicetree/aW+x9eA1I%2FnGdAL9@lizhi-Precision-Tower-5810/
https://lore.kernel.org/linux-devicetree/aYNkDWt89b26wJWf@lizhi-Precision-Tower-5810/
>
> > vpcie-supply = <®_pcie>;
>
> I would probably also take this chance to just convert to the proper PCI slot
> supply, and just add pwrctrl support into your PCIe driver.
Yes, this is my initial idea, you can find these info and my next step plan in the
patch set cover letter. This patch set adds the basic implementation to parse
Root Port device tree nodes first. Once the patches are accepted, I will start
work on the pwrctrl support. Thanks!
Best Regards
Sherry
>
>
> > status = "okay";
> > };
> >
> > +&pcie_port0 {
> > + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; };
> > +
> > &pwm1 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_pwm1>;
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > index 4dc2c410cf61..9438862b9927 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
> > @@ -302,6 +302,17 @@ pcie: pcie@1ffc000 {
> > <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> > clock-names = "pcie", "pcie_bus", "pcie_phy";
> > status = "disabled";
> > +
> > + pcie_port0: pcie@0 {
> > + compatible = "pciclass,0604";
> > + device_type = "pci";
> > + reg = <0x0 0x0 0x0 0x0 0x0>;
> > + bus-range = <0x01 0xff>;
> > +
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + ranges;
> > + };
> > };
> >
> > aips1: bus@2000000 { /* AIPS1 */ diff --git
> > a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > index c5b220aeaefd..6b12cab7175f 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
> > @@ -45,10 +45,15 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
> > };
> >
> > &pcie {
> > + /* This property is deprecated, use reset-gpios from the Root
> > + Port node. */
> > reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
> > status = "okay";
> > };
> >
> > +&pcie_port0 {
> > + reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>; };
> > +
> > &sata {
> > status = "okay";
> > };
> > --
> > 2.37.1
> >
> >
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property
2026-03-13 6:08 ` Chen-Yu Tsai
2026-03-13 7:16 ` Sherry Sun
@ 2026-03-16 5:30 ` Manivannan Sadhasivam
2026-03-17 8:14 ` Sherry Sun
1 sibling, 1 reply; 27+ messages in thread
From: Manivannan Sadhasivam @ 2026-03-16 5:30 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Sherry Sun, hongxing.zhu, l.stach, Frank.Li, bhelgaas,
lpieralisi, kwilczynski, robh, krzk+dt, conor+dt, s.hauer,
festevam, imx, kernel, linux-pci, linux-arm-kernel, devicetree,
linux-kernel
On Fri, Mar 13, 2026 at 02:08:05PM +0800, Chen-Yu Tsai wrote:
> On Fri, Mar 13, 2026 at 10:08 AM Sherry Sun <sherry.sun@nxp.com> wrote:
> >
> > Since describing the PCIe PERST# property under Host Bridge node is now
> > deprecated, it is recommended to add it to the Root Port node, so
> > creating the Root Port node and add the reset-gpios property in Root
> > Port.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++
> > arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++
> > arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++
> > 3 files changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > index ba29720e3f72..fe9046c03ddd 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > @@ -754,11 +754,16 @@ lvds0_out: endpoint {
> > &pcie {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_pcie>;
> > + /* This property is deprecated, use reset-gpios from the Root Port node. */
> > reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
>
> I'd say just remove the old description.
>
> You're asking for trouble by describing the same thing in two different places.
>
> > vpcie-supply = <®_pcie>;
>
> I would probably also take this chance to just convert to the proper PCI
> slot supply, and just add pwrctrl support into your PCIe driver.
>
+1
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property
2026-03-16 5:30 ` Manivannan Sadhasivam
@ 2026-03-17 8:14 ` Sherry Sun
0 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-17 8:14 UTC (permalink / raw)
To: Manivannan Sadhasivam, Chen-Yu Tsai
Cc: Hongxing Zhu, l.stach, Frank Li, bhelgaas, lpieralisi,
kwilczynski, robh, krzk+dt, conor+dt, s.hauer, festevam, imx,
kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
> Subject: Re: [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and
> PERST property
>
> On Fri, Mar 13, 2026 at 02:08:05PM +0800, Chen-Yu Tsai wrote:
> > On Fri, Mar 13, 2026 at 10:08 AM Sherry Sun <sherry.sun@nxp.com> wrote:
> > >
> > > Since describing the PCIe PERST# property under Host Bridge node is
> > > now deprecated, it is recommended to add it to the Root Port node,
> > > so creating the Root Port node and add the reset-gpios property in
> > > Root Port.
> > >
> > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > ---
> > > arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++
> > > arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++
> > > arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++
> > > 3 files changed, 21 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > index ba29720e3f72..fe9046c03ddd 100644
> > > --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
> > > @@ -754,11 +754,16 @@ lvds0_out: endpoint { &pcie {
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&pinctrl_pcie>;
> > > + /* This property is deprecated, use reset-gpios from the
> > > + Root Port node. */
> > > reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
> >
> > I'd say just remove the old description.
> >
> > You're asking for trouble by describing the same thing in two different
> places.
> >
> > > vpcie-supply = <®_pcie>;
> >
> > I would probably also take this chance to just convert to the proper
> > PCI slot supply, and just add pwrctrl support into your PCIe driver.
> >
>
> +1
Hi Mani,
Thanks for the comments, as I explained to Chen-Yu here, this patch set adds
the basic implementation to parse Root Port device tree nodes first. Once the
patches are finalized (the Root Port support model), I will start work on the
pwrctrl support. Thanks!
https://lore.kernel.org/linux-devicetree/VI0PR04MB12114A99A438C8E8749021AAD9245A@VI0PR04MB12114.eurprd04.prod.outlook.com/
Best Regards
Sherry
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V8 07/13] arm: dts: imx6sx: Add Root Port node and PERST property
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (5 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 2:08 ` [PATCH V8 08/13] arm: dts: imx7d: " Sherry Sun
` (5 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 5 +++++
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
index 3e238d8118fa..338de4d144b2 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
@@ -282,11 +282,16 @@ codec: wm8962@1a {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie_gpio>;
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+};
+
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
index 1426f357d474..d42363cb5105 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
@@ -1470,6 +1470,17 @@ pcie: pcie@8ffc000 {
power-domains = <&pd_disp>, <&pd_pci>;
power-domain-names = "pcie", "pcie_phy";
status = "disabled";
+
+ pcie_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
};
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V8 08/13] arm: dts: imx7d: Add Root Port node and PERST property
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (6 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 07/13] arm: dts: imx6sx: " Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 2:08 ` [PATCH V8 09/13] arm64: dts: imx8mm: " Sherry Sun
` (4 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts | 5 +++++
arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
index a370e868cafe..0046b276b8b9 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
@@ -456,10 +456,15 @@ display_out: endpoint {
};
&pcie {
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&extended_io 1 GPIO_ACTIVE_LOW>;
+};
+
®_1p0d {
vin-supply = <&sw2_reg>;
};
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
index d961c61a93af..3c5c1f2c1460 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
@@ -155,6 +155,17 @@ pcie: pcie@33800000 {
reset-names = "pciephy", "apps", "turnoff";
fsl,imx7d-pcie-phy = <&pcie_phy>;
status = "disabled";
+
+ pcie_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
};
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V8 09/13] arm64: dts: imx8mm: Add Root Port node and PERST property
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (7 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 08/13] arm: dts: imx7d: " Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 2:08 ` [PATCH V8 10/13] arm64: dts: imx8mp: " Sherry Sun
` (3 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 5 +++++
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 8be44eaf4e1e..e03aba825c18 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -533,6 +533,7 @@ &pcie_phy {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
@@ -559,6 +560,10 @@ &pcie0_ep {
status = "disabled";
};
+&pcie0_port0 {
+ reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+};
+
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index f2e1854f38a0..fa96432697ed 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1369,6 +1369,17 @@ pcie0: pcie@33800000 {
phys = <&pcie_phy>;
phy-names = "pcie-phy";
status = "disabled";
+
+ pcie0_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_ep: pcie-ep@33800000 {
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V8 10/13] arm64: dts: imx8mp: Add Root Port node and PERST property
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (8 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 09/13] arm64: dts: imx8mm: " Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 2:08 ` [PATCH V8 11/13] arm64: dts: imx8mq: " Sherry Sun
` (2 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 5 +++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index aedc09937716..9bdc8d000d2d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -769,6 +769,7 @@ &pcie_phy {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie0>;
vpcie3v3aux-supply = <®_pcie0>;
@@ -782,6 +783,10 @@ &pcie0_ep {
status = "disabled";
};
+&pcie0_port0 {
+ reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9b2b3a9bf9e8..f66667735a02 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -2266,6 +2266,17 @@ pcie0: pcie: pcie@33800000 {
phys = <&pcie_phy>;
phy-names = "pcie-phy";
status = "disabled";
+
+ pcie0_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_ep: pcie_ep: pcie-ep@33800000 {
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V8 11/13] arm64: dts: imx8mq: Add Root Port node and PERST property
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (9 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 10/13] arm64: dts: imx8mp: " Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 2:08 ` [PATCH V8 12/13] arm64: dts: imx8dxl/qm/qxp: " Sherry Sun
2026-03-13 2:08 ` [PATCH V8 13/13] arm64: dts: imx95: " Sherry Sun
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 +++++++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 22 ++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index d48f901487d4..e7d87ea81b69 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -369,6 +369,7 @@ mipi_dsi_out: endpoint {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&pcie0_refclk>,
@@ -389,9 +390,14 @@ &pcie0_ep {
status = "disabled";
};
+&pcie0_port0 {
+ reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
+};
+
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&pcie0_refclk>,
@@ -414,6 +420,10 @@ &pcie1_ep {
status = "disabled";
};
+&pcie1_port0 {
+ reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+};
+
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a25e219832c..e60872aeeb49 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1768,6 +1768,17 @@ pcie0: pcie@33800000 {
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
status = "disabled";
+
+ pcie0_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_ep: pcie-ep@33800000 {
@@ -1846,6 +1857,17 @@ pcie1: pcie@33c00000 {
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
status = "disabled";
+
+ pcie1_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_ep: pcie-ep@33c00000 {
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V8 12/13] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (10 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 11/13] arm64: dts: imx8mq: " Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
2026-03-13 2:08 ` [PATCH V8 13/13] arm64: dts: imx95: " Sherry Sun
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
.../boot/dts/freescale/imx8-ss-hsio.dtsi | 11 ++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 +++++
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 +++++++++
.../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 +++++
5 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
index 469de8b536b5..009990b2e559 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -78,6 +78,17 @@ pcieb: pcie@5f010000 {
power-domains = <&pd IMX_SC_R_PCIE_B>;
fsl,max-link-speed = <3>;
status = "disabled";
+
+ pcieb_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcieb_ep: pcie-ep@5f010000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 5c68d33e19f2..8f2c2bd00cde 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -651,6 +651,7 @@ &pcie0 {
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcieb>;
vpcie3v3aux-supply = <®_pcieb>;
@@ -667,6 +668,10 @@ &pcie0_ep {
status = "disabled";
};
+&pcieb_port0 {
+ reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+};
+
&sai0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai0>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index dadc136aec6e..02f7589bd860 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -802,6 +802,7 @@ &pciea {
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pciea>;
pinctrl-names = "default";
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pciea>;
vpcie3v3aux-supply = <®_pciea>;
@@ -809,15 +810,24 @@ &pciea {
status = "okay";
};
+&pciea_port0 {
+ reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
+};
+
&pcieb {
phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
status = "disabled";
};
+&pcieb_port0 {
+ reset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
+};
+
&qm_pwm_lvds0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_lvds0>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index f2c94cdb682b..2e4fbfe0ca16 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -41,6 +41,17 @@ pcie0: pciea: pcie@5f000000 {
power-domains = <&pd IMX_SC_R_PCIE_A>;
fsl,max-link-speed = <3>;
status = "disabled";
+
+ pciea_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_ep: pciea_ep: pcie-ep@5f000000 {
@@ -91,6 +102,17 @@ pcie1: pcieb: pcie@5f010000 {
power-domains = <&pd IMX_SC_R_PCIE_B>;
fsl,max-link-speed = <3>;
status = "disabled";
+
+ pcieb_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
sata: sata@5f020000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 40a0bc9f4e84..cd127d0a0a75 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -722,6 +722,7 @@ &pcie0 {
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcieb>;
vpcie3v3aux-supply = <®_pcieb>;
@@ -738,6 +739,10 @@ &pcie0_ep {
status = "disabled";
};
+&pcieb_port0 {
+ reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+};
+
&scu_key {
status = "okay";
};
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V8 13/13] arm64: dts: imx95: Add Root Port node and PERST property
2026-03-13 2:08 [PATCH V8 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding Sherry Sun
` (11 preceding siblings ...)
2026-03-13 2:08 ` [PATCH V8 12/13] arm64: dts: imx8dxl/qm/qxp: " Sherry Sun
@ 2026-03-13 2:08 ` Sherry Sun
12 siblings, 0 replies; 27+ messages in thread
From: Sherry Sun @ 2026-03-13 2:08 UTC (permalink / raw)
To: hongxing.zhu, l.stach, Frank.Li, bhelgaas, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, s.hauer, festevam
Cc: imx, kernel, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
.../boot/dts/freescale/imx95-15x15-evk.dts | 5 +++++
.../boot/dts/freescale/imx95-19x19-evk.dts | 10 +++++++++
arch/arm64/boot/dts/freescale/imx95.dtsi | 22 +++++++++++++++++++
3 files changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index d4184fb8b28c..42bc09e48b80 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
@@ -554,6 +554,7 @@ &netcmix_blk_ctrl {
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_m2_pwr>;
vpcie3v3aux-supply = <®_m2_pwr>;
@@ -568,6 +569,10 @@ &pcie0_ep {
status = "disabled";
};
+&pcie0_port0 {
+ reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+};
+
&sai1 {
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 041fd838fabb..6f193cf04119 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -540,6 +540,7 @@ &netc_timer {
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie0>;
vpcie3v3aux-supply = <®_pcie0>;
@@ -554,9 +555,14 @@ &pcie0_ep {
status = "disabled";
};
+&pcie0_port0 {
+ reset-gpios = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
+};
+
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_slot_pwr>;
vpcie3v3aux-supply = <®_slot_pwr>;
@@ -570,6 +576,10 @@ &pcie1_ep {
status = "disabled";
};
+&pcie1_port0 {
+ reset-gpios = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
+};
+
&sai1 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 5f61866e9df9..752236afce11 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1890,6 +1890,17 @@ pcie0: pcie@4c300000 {
iommu-map-mask = <0x1ff>;
fsl,max-link-speed = <3>;
status = "disabled";
+
+ pcie0_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_ep: pcie-ep@4c300000 {
@@ -1967,6 +1978,17 @@ pcie1: pcie@4c380000 {
iommu-map-mask = <0x1ff>;
fsl,max-link-speed = <3>;
status = "disabled";
+
+ pcie1_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_ep: pcie-ep@4c380000 {
--
2.37.1
^ permalink raw reply [flat|nested] 27+ messages in thread