[PATCH 0/6] arm64: dts: broadcom: bcm2712: add missing nodes

[PATCH 0/6] arm64: dts: broadcom: bcm2712: add missing nodes

[Gregor Herburger]

Hi,

This series addresses some missing nodes for the bcm2712 raspberry pi 5
and includes some fixes for the -d revision.
I identified these while working on the camera interfaces on the
rapsberry pi 5. All the drivers were already there. Only the devicetree
nodes were missing.
As I don't have access to any datasheets, these changes were ported from
the downstream tree (https://github.com/raspberrypi/linux/).

---
Gregor Herburger (6):
      arm64: dts: broadcom: rp1: add i2c controller
      arm64: dts: broadcom: rp1: add csi nodes
      arm64: dts: broadcom: bcm2712: add camera backend node pispbe
      arm64: dts: broadcom: bcm2712-rpi-5-b: add pinctrl properties for csi i2cs
      arm64: dts: broadcom: bcm2712-d-rpi-5-b: add fixes for pinctrl/pinctrl_aon
      arm64: dts: broadcom: bcm2712-d-rpi-5-b: update uart10 interrupt

 arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts |  14 +++
 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts   |  24 +++++
 arch/arm64/boot/dts/broadcom/bcm2712.dtsi          |   7 ++
 arch/arm64/boot/dts/broadcom/rp1-common.dtsi       | 105 +++++++++++++++++++++
 4 files changed, 150 insertions(+)
---
base-commit: 44982d352c33767cd8d19f8044e7e1161a587ff7
change-id: 20260220-raspi-dts-updates-cb11bf3f8742

Best regards,
-- 
Gregor Herburger <gregor.herburger@linutronix.de>

[PATCH 1/6] arm64: dts: broadcom: rp1: add i2c controller

[Gregor Herburger]

The RaspberryPi 5 has 7 designware-i2c I2C controller on the RP1
chipset.

Add the relevant nodes to the devicetree.

Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
---
 arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 77 ++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
index 5a815c379794524de542a62e7b157fbefe4b4b59..58179094e30e7e0eb6242de9edc460fd4a0b7685 100644
--- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
+++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
@@ -26,6 +26,83 @@ rp1_clocks: clocks@40018000 {
 				       <200000000>;  // RP1_CLK_SYS
 	};
 
+	rp1_i2c0: i2c@40070000 {
+		compatible = "snps,designware-i2c";
+		reg = <0x0 0x40070000  0x0 0x1000>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_SYS>;
+		i2c-scl-rising-time-ns = <65>;
+		i2c-scl-falling-time-ns = <100>;
+
+		status = "disabled";
+	};
+
+	rp1_i2c1: i2c@40074000 {
+		compatible = "snps,designware-i2c";
+		reg = <0x0 0x40074000  0x0 0x1000>;
+		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_SYS>;
+		i2c-scl-rising-time-ns = <65>;
+		i2c-scl-falling-time-ns = <100>;
+
+		status = "disabled";
+	};
+
+	rp1_i2c2: i2c@40078000 {
+		compatible = "snps,designware-i2c";
+		reg = <0x0 0x40078000  0x0 0x1000>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_SYS>;
+		i2c-scl-rising-time-ns = <65>;
+		i2c-scl-falling-time-ns = <100>;
+
+		status = "disabled";
+	};
+
+	rp1_i2c3: i2c@4007c000 {
+		compatible = "snps,designware-i2c";
+		reg = <0x0 0x4007c000  0x0 0x1000>;
+		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_SYS>;
+		i2c-scl-rising-time-ns = <65>;
+		i2c-scl-falling-time-ns = <100>;
+
+		status = "disabled";
+	};
+
+	rp1_i2c4: i2c@40080000 {
+		compatible = "snps,designware-i2c";
+		reg = <0x0 0x40080000  0x0 0x1000>;
+		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_SYS>;
+		i2c-scl-rising-time-ns = <65>;
+		i2c-scl-falling-time-ns = <100>;
+
+		status = "disabled";
+	};
+
+	rp1_i2c5: i2c@40084000 {
+		compatible = "snps,designware-i2c";
+		reg = <0x0 0x40084000  0x0 0x1000>;
+		interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_SYS>;
+		i2c-scl-rising-time-ns = <65>;
+		i2c-scl-falling-time-ns = <100>;
+
+		status = "disabled";
+	};
+
+	rp1_i2c6: i2c@40088000 {
+		compatible = "snps,designware-i2c";
+		reg = <0x0 0x40088000  0x0 0x1000>;
+		interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_SYS>;
+		i2c-scl-rising-time-ns = <65>;
+		i2c-scl-falling-time-ns = <100>;
+
+		status = "disabled";
+	};
+
 	rp1_gpio: pinctrl@400d0000 {
 		compatible = "raspberrypi,rp1-gpio";
 		reg = <0x00 0x400d0000  0x0 0xc000>,

-- 
2.47.3

[PATCH 2/6] arm64: dts: broadcom: rp1: add csi nodes

[Gregor Herburger]

The RaspberryPi 5 has 2 PiSP Camera front end controller on the RP1
chipset.

Add the relevant nodes to the devicetree.

Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
---
 arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
index 58179094e30e7e0eb6242de9edc460fd4a0b7685..16f5359395835f7a145aad75094d525e10dcd2ca 100644
--- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
+++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
@@ -133,6 +133,34 @@ rp1_eth: ethernet@40100000 {
 		#size-cells = <0>;
 	};
 
+	rp1_csi0: csi@40110000 {
+		compatible = "raspberrypi,rp1-cfe";
+		reg = <0x0 0x40110000  0x0 0x100>, // CSI2 DMA address
+		      <0x0 0x40114000  0x0 0x100>, // PHY/CSI Host address
+		      <0x0 0x40120000  0x0 0x100>, // MIPI CFG address
+		      <0x0 0x40124000  0x0 0x1000>; // PiSP FE address
+		interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
+		assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
+		assigned-clock-rates = <25000000>;
+
+		status = "disabled";
+	};
+
+	rp1_csi1: csi@40128000 {
+		compatible = "raspberrypi,rp1-cfe";
+		reg = <0x0 0x40128000  0x0 0x100>, // CSI2 DMA address
+		      <0x0 0x4012c000  0x0 0x100>, // PHY/CSI Host address
+		      <0x0 0x40138000  0x0 0x100>, // MIPI CFG address
+		      <0x0 0x4013c000  0x0 0x1000>; // PiSP FE address
+		interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
+		assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
+		assigned-clock-rates = <25000000>;
+
+		status = "disabled";
+	};
+
 	rp1_usb0: usb@40200000 {
 		compatible = "snps,dwc3";
 		reg = <0x00 0x40200000  0x0 0x100000>;

-- 
2.47.3

[PATCH 3/6] arm64: dts: broadcom: bcm2712: add camera backend node pispbe

[Gregor Herburger]

The bcm2712 found in the Raspberry Pi 5 has a PiSP Image Signal
Processor back end image processor.

Add the relevant node to the devicetree.

Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
---
 arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 69bd2934b93b34fef27989f9ddcd8a860979ab5f..98cb2173137ecda89d7f7ca1456598ff27231196 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -648,6 +648,13 @@ mip1: msi-controller@1000131000 {
 			brcm,msi-offset = <8>;
 		};
 
+		isp: isp@1000880000  {
+		     compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe";
+		     reg = <0x10 0x00880000 0x0 0x4000>;
+		     interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+		     clocks = <&firmware_clocks 7>;
+		};
+
 		v3d: gpu@1002000000 {
 			compatible = "brcm,2712-v3d";
 			reg = <0x10 0x02000000 0x00 0x4000>,

-- 
2.47.3

[PATCH 4/6] arm64: dts: broadcom: bcm2712-rpi-5-b: add pinctrl properties for csi i2cs

[Gregor Herburger]

Configure the i2c pins for the csi interfaces as i2c.

Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
---
 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
index 28560828144622622e610db12fbacbf1a6b7267a..0fc57e72632edca4686a859520a0dce7ff112f06 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -68,6 +68,30 @@ usb_vbus_default_state: usb-vbus-default-state {
 		function = "vbus1";
 		groups = "vbus1";
 	};
+
+	rp1_i2c4_default_state: rp1-i2c4-default-state {
+		function = "i2c4";
+		groups = "i2c4_2";
+		drive-strength = <12>;
+		bias-pull-up;
+	};
+
+	rp1_i2c6_default_state: rp1-i2c6-default-state {
+		function = "i2c6";
+		groups = "i2c6_0";
+		drive-strength = <12>;
+		bias-pull-up;
+	};
+};
+
+&rp1_i2c4 {
+	pinctrl-0 = <&rp1_i2c4_default_state>;
+	pinctrl-names = "default";
+};
+
+&rp1_i2c6 {
+	pinctrl-0 = <&rp1_i2c6_default_state>;
+	pinctrl-names = "default";
 };
 
 &rp1_usb0 {

-- 
2.47.3

[PATCH 5/6] arm64: dts: broadcom: bcm2712-d-rpi-5-b: add fixes for pinctrl/pinctrl_aon

[Gregor Herburger]

On the -d revision of the bcm2712 the pinctrl differs from the c0
revision. The driver already supports both and distinguishes the two
with the compatible string.

Update the compatible string and reg length to reflect the different
pinctrl.

Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
---
 arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts
index 7de24d60bcd1a7273ecc4eb814694183bb41c624..cbfc82d884c8268624682e9a49bda1feae34cbed 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts
@@ -35,3 +35,13 @@ &gio_aon {
 		"PMIC_SCL", // AON_SGPIO_04
 		"PMIC_SDA"; // AON_SGPIO_05
 };
+
+&pinctrl {
+	compatible = "brcm,bcm2712d0-pinctrl";
+	reg = <0x7d504100 0x20>;
+};
+
+&pinctrl_aon {
+	compatible = "brcm,bcm2712d0-aon-pinctrl";
+	reg = <0x7d510700 0x1c>;
+};

-- 
2.47.3

[PATCH 6/6] arm64: dts: broadcom: bcm2712-d-rpi-5-b: update uart10 interrupt

[Gregor Herburger]

On the -d revision of bcm2712 the uart interrupt is on 120. Update it
accordingly.

Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
---
 arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts
index cbfc82d884c8268624682e9a49bda1feae34cbed..127be0fc27c22e73b0cfdbfb89963cd3edf7594a 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts
@@ -45,3 +45,7 @@ &pinctrl_aon {
 	compatible = "brcm,bcm2712d0-aon-pinctrl";
 	reg = <0x7d510700 0x1c>;
 };
+
+&uart10 {
+	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+};

-- 
2.47.3

Re: [PATCH 1/6] arm64: dts: broadcom: rp1: add i2c controller

[Florian Fainelli]

From: Florian Fainelli <f.fainelli@gmail.com>

On Thu, 26 Feb 2026 09:55:54 +0100, Gregor Herburger <gregor.herburger@linutronix.de> wrote:
> The RaspberryPi 5 has 7 designware-i2c I2C controller on the RP1
> chipset.
> 
> Add the relevant nodes to the devicetree.
> 
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---

Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian

Re: [PATCH 2/6] arm64: dts: broadcom: rp1: add csi nodes

[Florian Fainelli]

From: Florian Fainelli <f.fainelli@gmail.com>

On Thu, 26 Feb 2026 09:55:55 +0100, Gregor Herburger <gregor.herburger@linutronix.de> wrote:
> The RaspberryPi 5 has 2 PiSP Camera front end controller on the RP1
> chipset.
> 
> Add the relevant nodes to the devicetree.
> 
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---

Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian

Re: [PATCH 3/6] arm64: dts: broadcom: bcm2712: add camera backend node pispbe

[Florian Fainelli]

From: Florian Fainelli <f.fainelli@gmail.com>

On Thu, 26 Feb 2026 09:55:56 +0100, Gregor Herburger <gregor.herburger@linutronix.de> wrote:
> The bcm2712 found in the Raspberry Pi 5 has a PiSP Image Signal
> Processor back end image processor.
> 
> Add the relevant node to the devicetree.
> 
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---

Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian

Re: [PATCH 4/6] arm64: dts: broadcom: bcm2712-rpi-5-b: add pinctrl properties for csi i2cs

[Florian Fainelli]

From: Florian Fainelli <f.fainelli@gmail.com>

On Thu, 26 Feb 2026 09:55:57 +0100, Gregor Herburger <gregor.herburger@linutronix.de> wrote:
> Configure the i2c pins for the csi interfaces as i2c.
> 
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---

Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian

Re: [PATCH 5/6] arm64: dts: broadcom: bcm2712-d-rpi-5-b: add fixes for pinctrl/pinctrl_aon

[Florian Fainelli]

From: Florian Fainelli <f.fainelli@gmail.com>

On Thu, 26 Feb 2026 09:55:58 +0100, Gregor Herburger <gregor.herburger@linutronix.de> wrote:
> On the -d revision of the bcm2712 the pinctrl differs from the c0
> revision. The driver already supports both and distinguishes the two
> with the compatible string.
> 
> Update the compatible string and reg length to reflect the different
> pinctrl.
> 
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---

Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian

Re: [PATCH 6/6] arm64: dts: broadcom: bcm2712-d-rpi-5-b: update uart10 interrupt

[Florian Fainelli]

From: Florian Fainelli <f.fainelli@gmail.com>

On Thu, 26 Feb 2026 09:55:59 +0100, Gregor Herburger <gregor.herburger@linutronix.de> wrote:
> On the -d revision of bcm2712 the uart interrupt is on 120. Update it
> accordingly.
> 
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---

Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian