[PATCH 5/5] arm64: dts: arm/corstone1000: Add corstone-1000-a320

["Rob Herring (Arm)" <robh@kernel.org>]

The Corstone-1000-a320 is a Corstone-1000 derivative with Cortex-A320 cores,
GIC-600, and Ethos-U85 NPU.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
 arch/arm64/boot/dts/arm/Makefile                  |  1 +
 arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts | 15 ++++
 arch/arm64/boot/dts/arm/corstone1000-a320.dtsi    | 91 +++++++++++++++++++++++
 3 files changed, 107 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index f30ee045dc95..fa035c68991a 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -7,4 +7,5 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-a320-fvp.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb
diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts
new file mode 100644
index 000000000000..0f72af78b5e1
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2026, Arm Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000-a320.dtsi"
+#include "corstone1000-fvp.dtsi"
+
+/ {
+	model = "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)";
+	compatible = "arm,corstone1000-a320-fvp";
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
new file mode 100644
index 000000000000..f0937914350c
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2026, Arm Limited. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "corstone1000.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus: cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a320";
+			reg = <0 0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a320";
+			reg = <0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a320";
+			reg = <0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a320";
+			reg = <0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	sram: sram@2400000 {
+		compatible = "mmio-sram";
+		reg = <0x02400000 0x200000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+	};
+
+	gic: interrupt-controller@1c000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-controller;
+		reg = <0x1c000000 0x10000>,
+		      <0x1c040000 0x80000>;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+
+	soc {
+		npu@1a050000 {
+			compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85";
+			reg = <0x1a050000 0x1400>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&refclk100mhz>, <&refclk100mhz>;
+			clock-names = "core", "apb";
+			sram = <&sram>;
+		};
+	};
+};

-- 
2.51.0