* [PATCH v1] dmaengine: dw-edma: Add Xilinx CPM6-DMA DeviceID
@ 2026-06-03 14:31 Devendra K Verma
2026-06-04 19:48 ` Frank Li
0 siblings, 1 reply; 3+ messages in thread
From: Devendra K Verma @ 2026-06-03 14:31 UTC (permalink / raw)
To: bhelgaas, mani, vkoul
Cc: dmaengine, linux-pci, linux-kernel, michal.simek, Devendra.Verma
From: Devendra K Verma <devverma@amd.com>
Add Device ID for AMD (Xilinx) CPM6 DMA IP.
This IP enables 64 Read and 64 Write Channels.
Adding the relevant dw_edma_pcie_data to use
8 Read and 8 Write Channels for initial commit.
Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
---
drivers/dma/dw-edma/dw-edma-pcie.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
index 0b30ce138503..4ba368d18cb1 100644
--- a/drivers/dma/dw-edma/dw-edma-pcie.c
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -27,6 +27,7 @@
/* AMD MDB (Xilinx) specific defines */
#define PCI_DEVICE_ID_XILINX_B054 0xb054
+#define PCI_DEVICE_ID_XILINX_B00F 0xb00f
#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6
#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20
@@ -125,6 +126,19 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = {
.rd_ch_cnt = 8,
};
+static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = {
+ /* MDB registers location */
+ .rg.bar = BAR_0,
+ .rg.off = SZ_4K, /* 4 Kbytes */
+ .rg.sz = SZ_8K, /* 8 Kbytes */
+
+ /* Other */
+ .mf = EDMA_MF_HDMA_NATIVE,
+ .irqs = 1,
+ .wr_ch_cnt = 8,
+ .rd_ch_cnt = 8,
+};
+
static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata,
enum pci_barno bar, off_t start_off,
off_t ll_off_gap, size_t ll_size,
@@ -547,6 +561,8 @@ static const struct pci_device_id dw_edma_pcie_id_table[] = {
{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054),
(kernel_ulong_t)&xilinx_mdb_data },
+ { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B00F),
+ (kernel_ulong_t)&xilinx_cpm6_dma_data },
{ }
};
MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
--
2.43.0
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] dmaengine: dw-edma: Add Xilinx CPM6-DMA DeviceID
2026-06-03 14:31 [PATCH v1] dmaengine: dw-edma: Add Xilinx CPM6-DMA DeviceID Devendra K Verma
@ 2026-06-04 19:48 ` Frank Li
2026-06-05 11:28 ` Verma, Devendra
0 siblings, 1 reply; 3+ messages in thread
From: Frank Li @ 2026-06-04 19:48 UTC (permalink / raw)
To: Devendra K Verma
Cc: bhelgaas, mani, vkoul, dmaengine, linux-pci, linux-kernel, michal.simek
On Wed, Jun 03, 2026 at 08:01:58PM +0530, Devendra K Verma wrote:
> From: Devendra K Verma <devverma@amd.com>
>
> Add Device ID for AMD (Xilinx) CPM6 DMA IP.
> This IP enables 64 Read and 64 Write Channels.
>
> Adding the relevant dw_edma_pcie_data to use
> 8 Read and 8 Write Channels for initial commit.
Nit: wrap at 75 char
>
> Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
> ---
> drivers/dma/dw-edma/dw-edma-pcie.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
> index 0b30ce138503..4ba368d18cb1 100644
> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c
> @@ -27,6 +27,7 @@
>
> /* AMD MDB (Xilinx) specific defines */
> #define PCI_DEVICE_ID_XILINX_B054 0xb054
> +#define PCI_DEVICE_ID_XILINX_B00F 0xb00f
>
> #define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6
> #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20
> @@ -125,6 +126,19 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = {
> .rd_ch_cnt = 8,
> };
>
> +static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = {
> + /* MDB registers location */
> + .rg.bar = BAR_0,
> + .rg.off = SZ_4K, /* 4 Kbytes */
> + .rg.sz = SZ_8K, /* 8 Kbytes */
> +
> + /* Other */
> + .mf = EDMA_MF_HDMA_NATIVE,
> + .irqs = 1,
> + .wr_ch_cnt = 8,
> + .rd_ch_cnt = 8,
> +};
> +
> static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata,
> enum pci_barno bar, off_t start_off,
> off_t ll_off_gap, size_t ll_size,
> @@ -547,6 +561,8 @@ static const struct pci_device_id dw_edma_pcie_id_table[] = {
> { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
> { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054),
> (kernel_ulong_t)&xilinx_mdb_data },
> + { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B00F),
> + (kernel_ulong_t)&xilinx_cpm6_dma_data },
Please .driver_data = (kernel_ulong_t)&xilinx_cpm6_dma_data
Now Uwe Kleine-König is cleanup this.
See similar thread
https://lore.kernel.org/linux-i3c/20260504143324.2122737-2-u.kleine-koenig@baylibre.com/
Frank
> { }
> };
> MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v1] dmaengine: dw-edma: Add Xilinx CPM6-DMA DeviceID
2026-06-04 19:48 ` Frank Li
@ 2026-06-05 11:28 ` Verma, Devendra
0 siblings, 0 replies; 3+ messages in thread
From: Verma, Devendra @ 2026-06-05 11:28 UTC (permalink / raw)
To: Frank Li
Cc: bhelgaas, mani, vkoul, dmaengine, linux-pci, linux-kernel, Simek, Michal
AMD General
> -----Original Message-----
> From: Frank Li <Frank.li@nxp.com>
> Sent: Friday, June 5, 2026 01:18
> To: Verma, Devendra <Devendra.Verma@amd.com>
> Cc: bhelgaas@google.com; mani@kernel.org; vkoul@kernel.org;
> dmaengine@vger.kernel.org; linux-pci@vger.kernel.org; linux-
> kernel@vger.kernel.org; Simek, Michal <michal.simek@amd.com>
> Subject: Re: [PATCH v1] dmaengine: dw-edma: Add Xilinx CPM6-DMA
> DeviceID
>
> On Wed, Jun 03, 2026 at 08:01:58PM +0530, Devendra K Verma wrote:
> > From: Devendra K Verma <devverma@amd.com>
> >
> > Add Device ID for AMD (Xilinx) CPM6 DMA IP.
> > This IP enables 64 Read and 64 Write Channels.
> >
> > Adding the relevant dw_edma_pcie_data to use
> > 8 Read and 8 Write Channels for initial commit.
>
> Nit: wrap at 75 char
Will be taken care in v2.
>
> >
> > Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
> > ---
> > drivers/dma/dw-edma/dw-edma-pcie.c | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c
> > b/drivers/dma/dw-edma/dw-edma-pcie.c
> > index 0b30ce138503..4ba368d18cb1 100644
> > --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> > +++ b/drivers/dma/dw-edma/dw-edma-pcie.c
> > @@ -27,6 +27,7 @@
> >
> > /* AMD MDB (Xilinx) specific defines */
> > #define PCI_DEVICE_ID_XILINX_B054 0xb054
> > +#define PCI_DEVICE_ID_XILINX_B00F 0xb00f
> >
> > #define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6
> > #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20
> > @@ -125,6 +126,19 @@ static const struct dw_edma_pcie_data
> xilinx_mdb_data = {
> > .rd_ch_cnt = 8,
> > };
> >
> > +static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = {
> > + /* MDB registers location */
> > + .rg.bar = BAR_0,
> > + .rg.off = SZ_4K, /* 4 Kbytes */
> > + .rg.sz = SZ_8K, /* 8 Kbytes */
> > +
> > + /* Other */
> > + .mf = EDMA_MF_HDMA_NATIVE,
> > + .irqs = 1,
> > + .wr_ch_cnt = 8,
> > + .rd_ch_cnt = 8,
> > +};
> > +
> > static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data
> *pdata,
> > enum pci_barno bar, off_t start_off,
> > off_t ll_off_gap, size_t ll_size, @@ -
> 547,6 +561,8 @@ static
> > const struct pci_device_id dw_edma_pcie_id_table[] = {
> > { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
> > { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054),
> > (kernel_ulong_t)&xilinx_mdb_data },
> > + { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B00F),
> > + (kernel_ulong_t)&xilinx_cpm6_dma_data },
>
> Please .driver_data = (kernel_ulong_t)&xilinx_cpm6_dma_data
>
> Now Uwe Kleine-König is cleanup this.
>
> See similar thread
> https://lore.kernel.org/linux-i3c/20260504143324.2122737-2-u.kleine-
> koenig@baylibre.com/
>
> Frank
>
Thanks for the suggestion. Will push the v2 with recommended changes.
> > { }
> > };
> > MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-06-05 11:28 UTC | newest]
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2026-06-03 14:31 [PATCH v1] dmaengine: dw-edma: Add Xilinx CPM6-DMA DeviceID Devendra K Verma
2026-06-04 19:48 ` Frank Li
2026-06-05 11:28 ` Verma, Devendra
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