From: fuqiang wang <fuqiang.wng@gmail.com>
To: Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
Zenghui Yu <yuzenghui@huawei.com>,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev
Cc: dongxu zhang <xu910121@sina.com>,
wangfuqiang49 <wangfuqiang49@jd.com>,
fuqiang wang <fuqiang.wng@gmail.com>
Subject: [PATCH 1/2] arm64: Add MIDR_EL1 RES1 definitions
Date: Thu, 11 Jun 2026 17:09:33 +0800 [thread overview]
Message-ID: <20260611090934.84469-2-fuqiang.wng@gmail.com> (raw)
In-Reply-To: <20260611090934.84469-1-fuqiang.wng@gmail.com>
MIDR_EL1 bit 31 is RES1. Add named definitions for the bit.
Signed-off-by: fuqiang wang <fuqiang.wng@gmail.com>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 7b518e81dd15..4322b219f79a 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -39,6 +39,8 @@
#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
#define MIDR_IMPLEMENTOR(midr) \
(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
+#define MIDR_RES1_SHIFT 31
+#define MIDR_RES1_MASK (1 << MIDR_RES1_SHIFT)
#define MIDR_CPU_MODEL(imp, partnum) \
((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \
--
2.47.0
next prev parent reply other threads:[~2026-06-11 9:09 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 9:09 [PATCH 0/2] KVM: arm64: Fix MPIDR lookup for unreset vCPUs fuqiang wang
2026-06-11 9:09 ` fuqiang wang [this message]
2026-06-11 9:09 ` [PATCH 2/2] KVM: arm64: Skip unreset vCPUs in MPIDR lookup table fuqiang wang
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