From: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
To: Frank Li <Frank.Li@nxp.com>, Vinod Koul <vkoul@kernel.org>,
Angelo Dureghello <angelo@sysam.it>
Cc: Frank Li <Frank.Li@kernel.org>,
imx@lists.linux.dev, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org,
Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
Subject: [PATCH v3 0/5] dmaengine: mcf-edma: fix 64-channel handling and modernize IRQ setup
Date: Thu, 25 Jun 2026 10:59:36 +0200 [thread overview]
Message-ID: <20260625-b4-edma-dmaengine-v3-0-44be00ace37d@yoseli.org> (raw)
The MCF54418 ColdFire SoC integrates an enhanced DMA controller (eDMA)
with 64 DMA channels. The current mcf-edma interrupt and error handlers
only deal correctly with the first 32 channels: they test the status
bits with BIT(ch) on an "unsigned long", which is 32-bit on ColdFire, so
any access to a channel >= 32 is undefined behaviour and the
corresponding completions/errors are mishandled.
This series fixes the 64-channel handling and tidies up the related
code:
- move the shared eDMA error handler out of the header file so it can
be reused by the mcf-edma glue;
- add an FSL_EDMA_DRV_MCF driver flag to describe the ColdFire
specifics;
- fix the completion and error interrupt handlers to iterate over all
64 channels using a proper bitmap;
- register the per-channel interrupts with devm, which also fixes the
IRQ leak on the probe error path and quiesces the controller on
remove().
The two interrupt-handler fixes carry Fixes: tags and are candidates for
stable.
This work was previously posted as a single series together with the
ColdFire/m68k platform enablement. As the driver changes and the
arch/m68k/ enablement are independent and target different trees, they
are now sent separately.
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
Changes in v3:
- Rename the patch subject prefix dma: -> dmaengine: (Vinod Koul).
- Split the ColdFire/m68k enablement into its own series targeting the
m68k tree; this series now contains only the drivers/dma/ changes.
- Add Fixes: tags to the two 64-channel interrupt-handler fixes.
- Replace the "Add per-channel IRQ naming" change with a devm-based
per-channel IRQ registration that also fixes the probe-failure IRQ
leak and quiesces the controller on remove().
- Link to v2: https://lore.kernel.org/dmaengine/20251126-dma-coldfire-v2-0-5b1e4544d609@yoseli.org
---
Jean-Michel Hautbois (5):
dmaengine: fsl-edma: Move error handler out of header file
dmaengine: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA
dmaengine: mcf-edma: Fix interrupt handler for 64 DMA channels
dmaengine: mcf-edma: Fix error handler for all 64 DMA channels
dmaengine: mcf-edma: Use devm for per-channel IRQ registration
drivers/dma/fsl-edma-common.c | 5 ++
drivers/dma/fsl-edma-common.h | 11 ++--
drivers/dma/mcf-edma-main.c | 133 ++++++++++++++++++++----------------------
3 files changed, 72 insertions(+), 77 deletions(-)
---
base-commit: ab9de95c9cf952332ab79453b4b5d1bfca8e514f
change-id: 20260625-b4-edma-dmaengine-281c71664da7
Best regards,
--
Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
next reply other threads:[~2026-06-25 8:59 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-25 8:59 Jean-Michel Hautbois [this message]
2026-06-25 8:59 ` [PATCH v3 1/5] dmaengine: fsl-edma: Move error handler out of header file Jean-Michel Hautbois
2026-06-25 15:33 ` Frank Li
2026-06-25 8:59 ` [PATCH v3 2/5] dmaengine: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA Jean-Michel Hautbois
2026-06-25 15:16 ` Frank Li
2026-06-25 8:59 ` [PATCH v3 3/5] dmaengine: mcf-edma: Fix interrupt handler for 64 DMA channels Jean-Michel Hautbois
2026-06-25 15:30 ` Frank Li
2026-06-25 8:59 ` [PATCH v3 4/5] dmaengine: mcf-edma: Fix error handler for all " Jean-Michel Hautbois
2026-06-25 15:23 ` Frank Li
2026-06-25 8:59 ` [PATCH v3 5/5] dmaengine: mcf-edma: Use devm for per-channel IRQ registration Jean-Michel Hautbois
2026-06-25 15:26 ` Frank Li
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