From: Frank Li <Frank.li@oss.nxp.com>
To: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
Cc: Frank Li <Frank.Li@nxp.com>, Vinod Koul <vkoul@kernel.org>,
Angelo Dureghello <angelo@sysam.it>,
Frank Li <Frank.Li@kernel.org>,
imx@lists.linux.dev, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 5/5] dmaengine: mcf-edma: Use devm for per-channel IRQ registration
Date: Thu, 25 Jun 2026 11:26:02 -0400 [thread overview]
Message-ID: <aj1IimtQSmo9VNhQ@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20260625-b4-edma-dmaengine-v3-5-44be00ace37d@yoseli.org>
On Thu, Jun 25, 2026 at 10:59:41AM +0200, Jean-Michel Hautbois wrote:
> Register each eDMA transfer interrupt with a per-channel name
> ("eDMA-<n>") so /proc/interrupts and debugging tools can identify the
> channel behind each line, and switch the whole IRQ setup to
> devm_request_irq().
>
> Using the managed API lets devres release the handlers on probe
> failure or device removal, which removes the manual mcf_edma_irq_free()
> teardown and the IRQ leak / dangling irqaction that the previous error
> paths left behind. The devm_kasprintf() result is now checked for NULL
> before being used as the IRQ name.
>
> Because devres only frees the handlers after mcf_edma_remove() returns,
> the controller must be quiesced at the start of remove(): disable every
> channel's request and acknowledge any pending interrupt before tearing
> down the virtual channels. Otherwise an interrupt could fire into a
> partially torn-down state while the handlers are still registered.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/dma/mcf-edma-main.c | 84 ++++++++++++++++++++++-----------------------
> 1 file changed, 41 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
> index 3dab5d475d1b..119d49c829fb 100644
> --- a/drivers/dma/mcf-edma-main.c
> +++ b/drivers/dma/mcf-edma-main.c
> @@ -66,7 +66,7 @@ static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
> static int mcf_edma_irq_init(struct platform_device *pdev,
> struct fsl_edma_engine *mcf_edma)
> {
> - int ret = 0, i;
> + int ret, i, chan = 0;
> struct resource *res;
>
> res = platform_get_resource_byname(pdev,
> @@ -74,33 +74,47 @@ static int mcf_edma_irq_init(struct platform_device *pdev,
> if (!res)
> return -1;
>
> - for (ret = 0, i = res->start; i <= res->end; ++i)
> - ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
> - if (ret)
> - return ret;
> + for (i = res->start; i <= res->end; ++i) {
> + char *irq_name;
> +
> + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "eDMA-%d", chan++);
> + if (!irq_name)
> + return -ENOMEM;
> + ret = devm_request_irq(&pdev->dev, i, mcf_edma_tx_handler, 0,
> + irq_name, mcf_edma);
> + if (ret)
> + return ret;
> + }
>
> res = platform_get_resource_byname(pdev,
> IORESOURCE_IRQ, "edma-tx-16-55");
> if (!res)
> return -1;
>
> - for (ret = 0, i = res->start; i <= res->end; ++i)
> - ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
> - if (ret)
> - return ret;
> + for (i = res->start; i <= res->end; ++i) {
> + char *irq_name;
> +
> + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "eDMA-%d", chan++);
> + if (!irq_name)
> + return -ENOMEM;
> + ret = devm_request_irq(&pdev->dev, i, mcf_edma_tx_handler, 0,
> + irq_name, mcf_edma);
> + if (ret)
> + return ret;
> + }
>
> ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
> if (ret != -ENXIO) {
> - ret = request_irq(ret, mcf_edma_tx_handler,
> - 0, "eDMA", mcf_edma);
> + ret = devm_request_irq(&pdev->dev, ret, mcf_edma_tx_handler, 0,
> + "eDMA-tx-56-63", mcf_edma);
> if (ret)
> return ret;
> }
>
> ret = platform_get_irq_byname(pdev, "edma-err");
> if (ret != -ENXIO) {
> - ret = request_irq(ret, mcf_edma_err_handler,
> - 0, "eDMA", mcf_edma);
> + ret = devm_request_irq(&pdev->dev, ret, mcf_edma_err_handler, 0,
> + "eDMA-err", mcf_edma);
> if (ret)
> return ret;
> }
> @@ -108,35 +122,6 @@ static int mcf_edma_irq_init(struct platform_device *pdev,
> return 0;
> }
>
> -static void mcf_edma_irq_free(struct platform_device *pdev,
> - struct fsl_edma_engine *mcf_edma)
> -{
> - int irq;
> - struct resource *res;
> -
> - res = platform_get_resource_byname(pdev,
> - IORESOURCE_IRQ, "edma-tx-00-15");
> - if (res) {
> - for (irq = res->start; irq <= res->end; irq++)
> - free_irq(irq, mcf_edma);
> - }
> -
> - res = platform_get_resource_byname(pdev,
> - IORESOURCE_IRQ, "edma-tx-16-55");
> - if (res) {
> - for (irq = res->start; irq <= res->end; irq++)
> - free_irq(irq, mcf_edma);
> - }
> -
> - irq = platform_get_irq_byname(pdev, "edma-tx-56-63");
> - if (irq != -ENXIO)
> - free_irq(irq, mcf_edma);
> -
> - irq = platform_get_irq_byname(pdev, "edma-err");
> - if (irq != -ENXIO)
> - free_irq(irq, mcf_edma);
> -}
> -
> static struct fsl_edma_drvdata mcf_data = {
> .flags = FSL_EDMA_DRV_EDMA64 | FSL_EDMA_DRV_MCF,
> .setup_irq = mcf_edma_irq_init,
> @@ -249,8 +234,21 @@ static int mcf_edma_probe(struct platform_device *pdev)
> static void mcf_edma_remove(struct platform_device *pdev)
> {
> struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
> + struct edma_regs *regs = &mcf_edma->regs;
> + int i;
> +
> + /*
> + * The per-channel interrupts are requested with devm and are only
> + * freed after this function returns. Quiesce the controller first so
> + * that no interrupt can fire while the virtual channels are torn down:
> + * disable every channel's request and acknowledge any pending
> + * interrupt.
> + */
> + for (i = 0; i < mcf_edma->n_chans; i++)
> + fsl_edma_disable_request(&mcf_edma->chans[i]);
> + iowrite32(~0, regs->inth);
> + iowrite32(~0, regs->intl);
>
> - mcf_edma_irq_free(pdev, mcf_edma);
> fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
> dma_async_device_unregister(&mcf_edma->dma_dev);
> }
>
> --
> 2.39.5
>
prev parent reply other threads:[~2026-06-25 15:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-25 8:59 [PATCH v3 0/5] dmaengine: mcf-edma: fix 64-channel handling and modernize IRQ setup Jean-Michel Hautbois
2026-06-25 8:59 ` [PATCH v3 1/5] dmaengine: fsl-edma: Move error handler out of header file Jean-Michel Hautbois
2026-06-25 15:33 ` Frank Li
2026-06-25 8:59 ` [PATCH v3 2/5] dmaengine: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA Jean-Michel Hautbois
2026-06-25 15:16 ` Frank Li
2026-06-25 8:59 ` [PATCH v3 3/5] dmaengine: mcf-edma: Fix interrupt handler for 64 DMA channels Jean-Michel Hautbois
2026-06-25 15:30 ` Frank Li
2026-06-25 8:59 ` [PATCH v3 4/5] dmaengine: mcf-edma: Fix error handler for all " Jean-Michel Hautbois
2026-06-25 15:23 ` Frank Li
2026-06-25 8:59 ` [PATCH v3 5/5] dmaengine: mcf-edma: Use devm for per-channel IRQ registration Jean-Michel Hautbois
2026-06-25 15:26 ` Frank Li [this message]
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