* [PATCH v2 0/4] arm64: Fixes and cleanups for cpu-feature-registers.rst
@ 2026-07-02 19:11 Mark Brown
2026-07-02 19:11 ` [PATCH v2 1/4] arm64: Don't number registers in cpu-feature-registers.rst Mark Brown
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
Peter Maydell noticed some missing updates to cpu-feature-registers.rst,
while looking at these a number of other other omissions and some
maintainability problems were observed. Several registers and many
bitfields have not been added.
Following discussion with Catalin we remove the numbering of the
registers in the first patch so that when we add the registers we can
add them in a roughly sorted order, then fix up the missing
documentation before sorting the existing entries in the file.
This whole area should have much better tooling, rather than having to
update multiple places and manually cross check several different places
including rarely used documentation we should be marking up the sysreg
descriptions and then either generating the data or validating against
manually updated copies. Manually updated copies seem like a good idea
for the ABI documentation since while it's more work that would force
review. I did start on some sketches, it seemed like it might make
sense to tackle along with using the MRS but the libraries for that
seem not to be progressing at any great rate, I'll dig the sketches out.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Changes in v2:
- Remove documentation for hidden registers.
- Fix typos.
- Link to v1: https://patch.msgid.link/20260522-arm64-cpu-ftr-regs-v1-0-19775b40faf0@kernel.org
---
Mark Brown (4):
arm64: Don't number registers in cpu-feature-registers.rst
arm64: Document missing bitfields in cpu-feature-registers.rst
arm64: Sort registers in cpu-feature-registers.rst
arm64: Remove hidden bitfields from cpu-feature-registers.rst
Documentation/arch/arm64/cpu-feature-registers.rst | 593 +++++++++++++--------
1 file changed, 364 insertions(+), 229 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260521-arm64-cpu-ftr-regs-bceb2d34376f
Best regards,
--
Mark Brown <broonie@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/4] arm64: Don't number registers in cpu-feature-registers.rst
2026-07-02 19:11 [PATCH v2 0/4] arm64: Fixes and cleanups for cpu-feature-registers.rst Mark Brown
@ 2026-07-02 19:11 ` Mark Brown
2026-07-02 19:11 ` [PATCH v2 2/4] arm64: Document missing bitfields " Mark Brown
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
cpu-feature-regsters.rst documents the set of userspace visible ID
registers. At present the section for each register is numbered, this has
lead to the registers being documented in a haphazard order as new ones
have been added to the end of the list to avoid renumbering. Remove the
numbers so we can avoid this problem in future.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 26 +++++++++++-----------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index add66afc7b03..c6e5bc053c09 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -113,7 +113,7 @@ infrastructure:
4. List of registers with visible features
-------------------------------------------
- 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+ ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -146,7 +146,7 @@ infrastructure:
+------------------------------+---------+---------+
- 2) ID_AA64PFR0_EL1 - Processor Feature Register 0
+ ID_AA64PFR0_EL1 - Processor Feature Register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -173,7 +173,7 @@ infrastructure:
+------------------------------+---------+---------+
- 3) ID_AA64PFR1_EL1 - Processor Feature Register 1
+ ID_AA64PFR1_EL1 - Processor Feature Register 1
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -188,7 +188,7 @@ infrastructure:
+------------------------------+---------+---------+
- 4) MIDR_EL1 - Main ID Register
+ MIDR_EL1 - Main ID Register
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -208,7 +208,7 @@ infrastructure:
as available on the CPU where it is fetched and is not a system
wide safe value.
- 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+ ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -240,7 +240,7 @@ infrastructure:
| DPB | [3-0] | y |
+------------------------------+---------+---------+
- 6) ID_AA64MMFR0_EL1 - Memory model feature register 0
+ ID_AA64MMFR0_EL1 - Memory model feature register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -248,7 +248,7 @@ infrastructure:
| ECV | [63-60] | y |
+------------------------------+---------+---------+
- 7) ID_AA64MMFR2_EL1 - Memory model feature register 2
+ ID_AA64MMFR2_EL1 - Memory model feature register 2
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -256,7 +256,7 @@ infrastructure:
| AT | [35-32] | y |
+------------------------------+---------+---------+
- 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0
+ ID_AA64ZFR0_EL1 - SVE feature ID register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -282,7 +282,7 @@ infrastructure:
| SVEVer | [3-0] | y |
+------------------------------+---------+---------+
- 8) ID_AA64MMFR1_EL1 - Memory model feature register 1
+ ID_AA64MMFR1_EL1 - Memory model feature register 1
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -290,7 +290,7 @@ infrastructure:
| AFP | [47-44] | y |
+------------------------------+---------+---------+
- 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+ ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -312,7 +312,7 @@ infrastructure:
| WFXT | [3-0] | y |
+------------------------------+---------+---------+
- 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+ MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -320,7 +320,7 @@ infrastructure:
| FPDP | [11-8] | y |
+------------------------------+---------+---------+
- 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
+ MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -334,7 +334,7 @@ infrastructure:
| SIMDLS | [11-8] | y |
+------------------------------+---------+---------+
- 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+ ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+------------------------------+---------+---------+
| Name | bits | visible |
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/4] arm64: Document missing bitfields in cpu-feature-registers.rst
2026-07-02 19:11 [PATCH v2 0/4] arm64: Fixes and cleanups for cpu-feature-registers.rst Mark Brown
2026-07-02 19:11 ` [PATCH v2 1/4] arm64: Don't number registers in cpu-feature-registers.rst Mark Brown
@ 2026-07-02 19:11 ` Mark Brown
2026-07-02 19:11 ` [PATCH v2 3/4] arm64: Sort registers " Mark Brown
2026-07-02 19:11 ` [PATCH v2 4/4] arm64: Remove hidden bitfields from cpu-feature-registers.rst Mark Brown
3 siblings, 0 replies; 5+ messages in thread
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
We have been rather lax in updating the list of visible bitfields in the
ID registers in cpu-feature-registers.rst, it is currently missing several
of the registers and quite a few bitfields in existing registers. Bring it
into sync with current -next.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 146 +++++++++++++++++++++
1 file changed, 146 insertions(+)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index c6e5bc053c09..4b10980d4a40 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -113,6 +113,30 @@ infrastructure:
4. List of registers with visible features
-------------------------------------------
+ ID_AA64FPFR0_EL1 - Floating Point feature ID register 0
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | F8CVT | [31] | y |
+ +------------------------------+---------+---------+
+ | F8FMA | [30] | y |
+ +------------------------------+---------+---------+
+ | F8DP4 | [29] | y |
+ +------------------------------+---------+---------+
+ | F8DP2 | [28] | y |
+ +------------------------------+---------+---------+
+ | F8MM8 | [27] | y |
+ +------------------------------+---------+---------+
+ | F8MM4 | [26] | y |
+ +------------------------------+---------+---------+
+ | F16MM2 | [15] | y |
+ +------------------------------+---------+---------+
+ | F8E4M3 | [1] | y |
+ +------------------------------+---------+---------+
+ | F8E5M2 | [0] | y |
+ +------------------------------+---------+---------+
+
ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+------------------------------+---------+---------+
@@ -178,6 +202,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
+ | GCS | [47-44] | y |
+ +------------------------------+---------+---------+
| SME | [27-24] | y |
+------------------------------+---------+---------+
| MTE | [11-8] | y |
@@ -187,6 +213,17 @@ infrastructure:
| BT | [3-0] | y |
+------------------------------+---------+---------+
+ ID_AA64PFR2_EL1 - Processor Feature Register 2
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | FPMR | [35-32] | y |
+ +------------------------------+---------+---------+
+ | MTEFAR | [11-8] | y |
+ +------------------------------+---------+---------+
+ | MTESTOREONLY | [7-4] | y |
+ +------------------------------+---------+---------+
MIDR_EL1 - Main ID Register
@@ -213,6 +250,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
+ | LS64 | [63-60] | y |
+ +------------------------------+---------+---------+
| I8MM | [55-52] | y |
+------------------------------+---------+---------+
| DGH | [51-48] | y |
@@ -256,6 +295,68 @@ infrastructure:
| AT | [35-32] | y |
+------------------------------+---------+---------+
+ ID_AA64MMFR3_EL1 - Memory model feature register 3
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | S1POE | [19-16] | y |
+ +------------------------------+---------+---------+
+
+ ID_AA64SMFR0_EL1 - SME feature ID register 0
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | FA64 | [63] | y |
+ +------------------------------+---------+---------+
+ | LUT6 | [61] | y |
+ +------------------------------+---------+---------+
+ | LUTv2 | [60] | y |
+ +------------------------------+---------+---------+
+ | SMEver | [59-56] | y |
+ +------------------------------+---------+---------+
+ | I16I64 | [55-52] | y |
+ +------------------------------+---------+---------+
+ | F64F64 | [48] | y |
+ +------------------------------+---------+---------+
+ | I16I32 | [47-44] | y |
+ +------------------------------+---------+---------+
+ | B16B16 | [43] | y |
+ +------------------------------+---------+---------+
+ | F16F16 | [42] | y |
+ +------------------------------+---------+---------+
+ | F8F16 | [41] | y |
+ +------------------------------+---------+---------+
+ | F8F32 | [40] | y |
+ +------------------------------+---------+---------+
+ | I8I32 | [39-36] | y |
+ +------------------------------+---------+---------+
+ | F16F32 | [35] | y |
+ +------------------------------+---------+---------+
+ | B16F32 | [34] | y |
+ +------------------------------+---------+---------+
+ | BI32I32 | [33] | y |
+ +------------------------------+---------+---------+
+ | F32F32 | [32] | y |
+ +------------------------------+---------+---------+
+ | SF8FMA | [30] | y |
+ +------------------------------+---------+---------+
+ | SF8DP4 | [29] | y |
+ +------------------------------+---------+---------+
+ | SF8DP2 | [28] | y |
+ +------------------------------+---------+---------+
+ | SBitPerm | [25] | y |
+ +------------------------------+---------+---------+
+ | AES | [24] | y |
+ +------------------------------+---------+---------+
+ | SFEXPA | [23] | y |
+ +------------------------------+---------+---------+
+ | STMOP | [16] | y |
+ +------------------------------+---------+---------+
+ | SMOP4 | [0] | y |
+ +------------------------------+---------+---------+
+
ID_AA64ZFR0_EL1 - SVE feature ID register 0
+------------------------------+---------+---------+
@@ -265,6 +366,8 @@ infrastructure:
+------------------------------+---------+---------+
| F32MM | [55-52] | y |
+------------------------------+---------+---------+
+ | F16MM | [51-48] | y |
+ +------------------------------+---------+---------+
| I8MM | [47-44] | y |
+------------------------------+---------+---------+
| SM4 | [43-40] | y |
@@ -277,6 +380,8 @@ infrastructure:
+------------------------------+---------+---------+
| BitPerm | [19-16] | y |
+------------------------------+---------+---------+
+ | EltPerm | [15-12] | y |
+ +------------------------------+---------+---------+
| AES | [7-4] | y |
+------------------------------+---------+---------+
| SVEVer | [3-0] | y |
@@ -295,6 +400,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
+ | LUT | [59-56] | y |
+ +------------------------------+---------+---------+
| CSSC | [55-52] | y |
+------------------------------+---------+---------+
| RPRFM | [51-48] | y |
@@ -312,6 +419,18 @@ infrastructure:
| WFXT | [3-0] | y |
+------------------------------+---------+---------+
+ ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | FPRCVT | [31-28] | y |
+ +------------------------------+---------+---------+
+ | LSFE | [19-16] | y |
+ +------------------------------+---------+---------+
+ | FAMINMAX | [7-4] | y |
+ +------------------------------+---------+---------+
+
MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+------------------------------+---------+---------+
@@ -327,6 +446,10 @@ infrastructure:
+------------------------------+---------+---------+
| SIMDFMAC | [31-28] | y |
+------------------------------+---------+---------+
+ | FPHP | [27-24] | y |
+ +------------------------------+---------+---------+
+ | SIMDHP | [23-20] | y |
+ +------------------------------+---------+---------+
| SIMDSP | [19-16] | y |
+------------------------------+---------+---------+
| SIMDInt | [15-12] | y |
@@ -348,6 +471,29 @@ infrastructure:
| AES | [7-4] | y |
+------------------------------+---------+---------+
+ ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | I8MM | [27-24] | y |
+ +------------------------------+---------+---------+
+ | BF16 | [23-20] | y |
+ +------------------------------+---------+---------+
+ | SB | [15-12] | y |
+ +------------------------------+---------+---------+
+ | FHM | [11-8] | y |
+ +------------------------------+---------+---------+
+ | DP | [7-4] | y |
+ +------------------------------+---------+---------+
+
+ ID_PFR2_EL1 - AArch32 Processor Feature Register 2
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | SSBS | [7-4] | y |
+ +------------------------------+---------+---------+
Appendix I: Example
-------------------
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 3/4] arm64: Sort registers in cpu-feature-registers.rst
2026-07-02 19:11 [PATCH v2 0/4] arm64: Fixes and cleanups for cpu-feature-registers.rst Mark Brown
2026-07-02 19:11 ` [PATCH v2 1/4] arm64: Don't number registers in cpu-feature-registers.rst Mark Brown
2026-07-02 19:11 ` [PATCH v2 2/4] arm64: Document missing bitfields " Mark Brown
@ 2026-07-02 19:11 ` Mark Brown
2026-07-02 19:11 ` [PATCH v2 4/4] arm64: Remove hidden bitfields from cpu-feature-registers.rst Mark Brown
3 siblings, 0 replies; 5+ messages in thread
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
In order to make it a bit easier to work with sort the list of registers in
cpu-feature-registers.rst lexically. There should be no content changes
resulting from this patch.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 223 +++++++++++----------
1 file changed, 112 insertions(+), 111 deletions(-)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index 4b10980d4a40..683bdd90c705 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -170,137 +170,161 @@ infrastructure:
+------------------------------+---------+---------+
- ID_AA64PFR0_EL1 - Processor Feature Register 0
+ ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | DIT | [51-48] | y |
+ | LS64 | [63-60] | y |
+------------------------------+---------+---------+
- | MPAM | [43-40] | n |
+ | I8MM | [55-52] | y |
+------------------------------+---------+---------+
- | SVE | [35-32] | y |
+ | DGH | [51-48] | y |
+------------------------------+---------+---------+
- | GIC | [27-24] | n |
+ | BF16 | [47-44] | y |
+------------------------------+---------+---------+
- | AdvSIMD | [23-20] | y |
+ | SB | [39-36] | y |
+------------------------------+---------+---------+
- | FP | [19-16] | y |
+ | FRINTTS | [35-32] | y |
+------------------------------+---------+---------+
- | EL3 | [15-12] | n |
+ | GPI | [31-28] | y |
+------------------------------+---------+---------+
- | EL2 | [11-8] | n |
+ | GPA | [27-24] | y |
+------------------------------+---------+---------+
- | EL1 | [7-4] | n |
+ | LRCPC | [23-20] | y |
+------------------------------+---------+---------+
- | EL0 | [3-0] | n |
+ | FCMA | [19-16] | y |
+ +------------------------------+---------+---------+
+ | JSCVT | [15-12] | y |
+ +------------------------------+---------+---------+
+ | API | [11-8] | y |
+ +------------------------------+---------+---------+
+ | APA | [7-4] | y |
+ +------------------------------+---------+---------+
+ | DPB | [3-0] | y |
+------------------------------+---------+---------+
-
- ID_AA64PFR1_EL1 - Processor Feature Register 1
+ ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | GCS | [47-44] | y |
+ | LUT | [59-56] | y |
+------------------------------+---------+---------+
- | SME | [27-24] | y |
+ | CSSC | [55-52] | y |
+------------------------------+---------+---------+
- | MTE | [11-8] | y |
+ | RPRFM | [51-48] | y |
+------------------------------+---------+---------+
- | SSBS | [7-4] | y |
+ | BC | [23-20] | y |
+------------------------------+---------+---------+
- | BT | [3-0] | y |
+ | MOPS | [19-16] | y |
+ +------------------------------+---------+---------+
+ | APA3 | [15-12] | y |
+ +------------------------------+---------+---------+
+ | GPA3 | [11-8] | y |
+ +------------------------------+---------+---------+
+ | RPRES | [7-4] | y |
+ +------------------------------+---------+---------+
+ | WFXT | [3-0] | y |
+------------------------------+---------+---------+
- ID_AA64PFR2_EL1 - Processor Feature Register 2
+ ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | FPMR | [35-32] | y |
+ | FPRCVT | [31-28] | y |
+------------------------------+---------+---------+
- | MTEFAR | [11-8] | y |
+ | LSFE | [19-16] | y |
+------------------------------+---------+---------+
- | MTESTOREONLY | [7-4] | y |
+ | FAMINMAX | [7-4] | y |
+------------------------------+---------+---------+
- MIDR_EL1 - Main ID Register
+ ID_AA64MMFR0_EL1 - Memory model feature register 0
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | Implementer | [31-24] | y |
- +------------------------------+---------+---------+
- | Variant | [23-20] | y |
+ | ECV | [63-60] | y |
+------------------------------+---------+---------+
- | Architecture | [19-16] | y |
+
+ ID_AA64MMFR1_EL1 - Memory model feature register 1
+
+------------------------------+---------+---------+
- | PartNum | [15-4] | y |
+ | Name | bits | visible |
+------------------------------+---------+---------+
- | Revision | [3-0] | y |
+ | AFP | [47-44] | y |
+------------------------------+---------+---------+
- NOTE: The 'visible' fields of MIDR_EL1 will contain the value
- as available on the CPU where it is fetched and is not a system
- wide safe value.
-
- ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+ ID_AA64MMFR2_EL1 - Memory model feature register 2
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | LS64 | [63-60] | y |
+ | AT | [35-32] | y |
+------------------------------+---------+---------+
- | I8MM | [55-52] | y |
+
+ ID_AA64MMFR3_EL1 - Memory model feature register 3
+
+------------------------------+---------+---------+
- | DGH | [51-48] | y |
+ | Name | bits | visible |
+------------------------------+---------+---------+
- | BF16 | [47-44] | y |
+ | S1POE | [19-16] | y |
+------------------------------+---------+---------+
- | SB | [39-36] | y |
+
+ ID_AA64PFR0_EL1 - Processor Feature Register 0
+
+------------------------------+---------+---------+
- | FRINTTS | [35-32] | y |
+ | Name | bits | visible |
+------------------------------+---------+---------+
- | GPI | [31-28] | y |
+ | DIT | [51-48] | y |
+------------------------------+---------+---------+
- | GPA | [27-24] | y |
+ | MPAM | [43-40] | n |
+------------------------------+---------+---------+
- | LRCPC | [23-20] | y |
+ | SVE | [35-32] | y |
+------------------------------+---------+---------+
- | FCMA | [19-16] | y |
+ | GIC | [27-24] | n |
+------------------------------+---------+---------+
- | JSCVT | [15-12] | y |
+ | AdvSIMD | [23-20] | y |
+------------------------------+---------+---------+
- | API | [11-8] | y |
+ | FP | [19-16] | y |
+------------------------------+---------+---------+
- | APA | [7-4] | y |
+ | EL3 | [15-12] | n |
+------------------------------+---------+---------+
- | DPB | [3-0] | y |
+ | EL2 | [11-8] | n |
+ +------------------------------+---------+---------+
+ | EL1 | [7-4] | n |
+ +------------------------------+---------+---------+
+ | EL0 | [3-0] | n |
+------------------------------+---------+---------+
- ID_AA64MMFR0_EL1 - Memory model feature register 0
+
+ ID_AA64PFR1_EL1 - Processor Feature Register 1
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | ECV | [63-60] | y |
+ | GCS | [47-44] | y |
+------------------------------+---------+---------+
-
- ID_AA64MMFR2_EL1 - Memory model feature register 2
-
+ | SME | [27-24] | y |
+------------------------------+---------+---------+
- | Name | bits | visible |
+ | MTE | [11-8] | y |
+------------------------------+---------+---------+
- | AT | [35-32] | y |
+ | SSBS | [7-4] | y |
+ +------------------------------+---------+---------+
+ | BT | [3-0] | y |
+------------------------------+---------+---------+
- ID_AA64MMFR3_EL1 - Memory model feature register 3
+ ID_AA64PFR2_EL1 - Processor Feature Register 2
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | S1POE | [19-16] | y |
+ | FPMR | [35-32] | y |
+ +------------------------------+---------+---------+
+ | MTEFAR | [11-8] | y |
+ +------------------------------+---------+---------+
+ | MTESTOREONLY | [7-4] | y |
+------------------------------+---------+---------+
ID_AA64SMFR0_EL1 - SME feature ID register 0
@@ -387,50 +411,64 @@ infrastructure:
| SVEVer | [3-0] | y |
+------------------------------+---------+---------+
- ID_AA64MMFR1_EL1 - Memory model feature register 1
+ ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | AFP | [47-44] | y |
+ | CRC32 | [19-16] | y |
+ +------------------------------+---------+---------+
+ | SHA2 | [15-12] | y |
+ +------------------------------+---------+---------+
+ | SHA1 | [11-8] | y |
+ +------------------------------+---------+---------+
+ | AES | [7-4] | y |
+------------------------------+---------+---------+
- ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+ ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | LUT | [59-56] | y |
- +------------------------------+---------+---------+
- | CSSC | [55-52] | y |
+ | I8MM | [27-24] | y |
+------------------------------+---------+---------+
- | RPRFM | [51-48] | y |
+ | BF16 | [23-20] | y |
+------------------------------+---------+---------+
- | BC | [23-20] | y |
+ | SB | [15-12] | y |
+------------------------------+---------+---------+
- | MOPS | [19-16] | y |
+ | FHM | [11-8] | y |
+------------------------------+---------+---------+
- | APA3 | [15-12] | y |
+ | DP | [7-4] | y |
+------------------------------+---------+---------+
- | GPA3 | [11-8] | y |
+
+ ID_PFR2_EL1 - AArch32 Processor Feature Register 2
+
+------------------------------+---------+---------+
- | RPRES | [7-4] | y |
+ | Name | bits | visible |
+------------------------------+---------+---------+
- | WFXT | [3-0] | y |
+ | SSBS | [7-4] | y |
+------------------------------+---------+---------+
- ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+ MIDR_EL1 - Main ID Register
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | FPRCVT | [31-28] | y |
+ | Implementer | [31-24] | y |
+------------------------------+---------+---------+
- | LSFE | [19-16] | y |
+ | Variant | [23-20] | y |
+------------------------------+---------+---------+
- | FAMINMAX | [7-4] | y |
+ | Architecture | [19-16] | y |
+ +------------------------------+---------+---------+
+ | PartNum | [15-4] | y |
+ +------------------------------+---------+---------+
+ | Revision | [3-0] | y |
+------------------------------+---------+---------+
+ NOTE: The 'visible' fields of MIDR_EL1 will contain the value
+ as available on the CPU where it is fetched and is not a system
+ wide safe value.
+
MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+------------------------------+---------+---------+
@@ -457,43 +495,6 @@ infrastructure:
| SIMDLS | [11-8] | y |
+------------------------------+---------+---------+
- ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
-
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | CRC32 | [19-16] | y |
- +------------------------------+---------+---------+
- | SHA2 | [15-12] | y |
- +------------------------------+---------+---------+
- | SHA1 | [11-8] | y |
- +------------------------------+---------+---------+
- | AES | [7-4] | y |
- +------------------------------+---------+---------+
-
- ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
-
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | I8MM | [27-24] | y |
- +------------------------------+---------+---------+
- | BF16 | [23-20] | y |
- +------------------------------+---------+---------+
- | SB | [15-12] | y |
- +------------------------------+---------+---------+
- | FHM | [11-8] | y |
- +------------------------------+---------+---------+
- | DP | [7-4] | y |
- +------------------------------+---------+---------+
-
- ID_PFR2_EL1 - AArch32 Processor Feature Register 2
-
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | SSBS | [7-4] | y |
- +------------------------------+---------+---------+
Appendix I: Example
-------------------
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 4/4] arm64: Remove hidden bitfields from cpu-feature-registers.rst
2026-07-02 19:11 [PATCH v2 0/4] arm64: Fixes and cleanups for cpu-feature-registers.rst Mark Brown
` (2 preceding siblings ...)
2026-07-02 19:11 ` [PATCH v2 3/4] arm64: Sort registers " Mark Brown
@ 2026-07-02 19:11 ` Mark Brown
3 siblings, 0 replies; 5+ messages in thread
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
We currently have a visibility column in the tables for the registers in
cpu-feature-registers.rst but this is always "y" for every register other
than ID_AA64PFR0_EL1. Given that the documentation of the full set of
bitfields is readily available in the architecture documentation it is
redundant for us to explicitly document things we don't advertise, and the
kernel documentation will inevitably lag the architecture.
Just remove the visibility column and hidden bitfields.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 618 ++++++++++-----------
1 file changed, 303 insertions(+), 315 deletions(-)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index 683bdd90c705..fc63ccb666bf 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -115,355 +115,343 @@ infrastructure:
ID_AA64FPFR0_EL1 - Floating Point feature ID register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | F8CVT | [31] | y |
- +------------------------------+---------+---------+
- | F8FMA | [30] | y |
- +------------------------------+---------+---------+
- | F8DP4 | [29] | y |
- +------------------------------+---------+---------+
- | F8DP2 | [28] | y |
- +------------------------------+---------+---------+
- | F8MM8 | [27] | y |
- +------------------------------+---------+---------+
- | F8MM4 | [26] | y |
- +------------------------------+---------+---------+
- | F16MM2 | [15] | y |
- +------------------------------+---------+---------+
- | F8E4M3 | [1] | y |
- +------------------------------+---------+---------+
- | F8E5M2 | [0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | F8CVT | [31] |
+ +------------------------------+---------+
+ | F8FMA | [30] |
+ +------------------------------+---------+
+ | F8DP4 | [29] |
+ +------------------------------+---------+
+ | F8DP2 | [28] |
+ +------------------------------+---------+
+ | F8MM8 | [27] |
+ +------------------------------+---------+
+ | F8MM4 | [26] |
+ +------------------------------+---------+
+ | F16MM2 | [15] |
+ +------------------------------+---------+
+ | F8E4M3 | [1] |
+ +------------------------------+---------+
+ | F8E5M2 | [0] |
+ +------------------------------+---------+
ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | RNDR | [63-60] | y |
- +------------------------------+---------+---------+
- | TS | [55-52] | y |
- +------------------------------+---------+---------+
- | FHM | [51-48] | y |
- +------------------------------+---------+---------+
- | DP | [47-44] | y |
- +------------------------------+---------+---------+
- | SM4 | [43-40] | y |
- +------------------------------+---------+---------+
- | SM3 | [39-36] | y |
- +------------------------------+---------+---------+
- | SHA3 | [35-32] | y |
- +------------------------------+---------+---------+
- | RDM | [31-28] | y |
- +------------------------------+---------+---------+
- | ATOMICS | [23-20] | y |
- +------------------------------+---------+---------+
- | CRC32 | [19-16] | y |
- +------------------------------+---------+---------+
- | SHA2 | [15-12] | y |
- +------------------------------+---------+---------+
- | SHA1 | [11-8] | y |
- +------------------------------+---------+---------+
- | AES | [7-4] | y |
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | RNDR | [63-60] |
+ +------------------------------+---------+
+ | TS | [55-52] |
+ +------------------------------+---------+
+ | FHM | [51-48] |
+ +------------------------------+---------+
+ | DP | [47-44] |
+ +------------------------------+---------+
+ | SM4 | [43-40] |
+ +------------------------------+---------+
+ | SM3 | [39-36] |
+ +------------------------------+---------+
+ | SHA3 | [35-32] |
+ +------------------------------+---------+
+ | RDM | [31-28] |
+ +------------------------------+---------+
+ | ATOMICS | [23-20] |
+ +------------------------------+---------+
+ | CRC32 | [19-16] |
+ +------------------------------+---------+
+ | SHA2 | [15-12] |
+ +------------------------------+---------+
+ | SHA1 | [11-8] |
+ +------------------------------+---------+
+ | AES | [7-4] |
+------------------------------+---------+---------+
ID_AA64ISAR1_EL1 - Instruction set attribute register 1
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | LS64 | [63-60] | y |
- +------------------------------+---------+---------+
- | I8MM | [55-52] | y |
- +------------------------------+---------+---------+
- | DGH | [51-48] | y |
- +------------------------------+---------+---------+
- | BF16 | [47-44] | y |
- +------------------------------+---------+---------+
- | SB | [39-36] | y |
- +------------------------------+---------+---------+
- | FRINTTS | [35-32] | y |
- +------------------------------+---------+---------+
- | GPI | [31-28] | y |
- +------------------------------+---------+---------+
- | GPA | [27-24] | y |
- +------------------------------+---------+---------+
- | LRCPC | [23-20] | y |
- +------------------------------+---------+---------+
- | FCMA | [19-16] | y |
- +------------------------------+---------+---------+
- | JSCVT | [15-12] | y |
- +------------------------------+---------+---------+
- | API | [11-8] | y |
- +------------------------------+---------+---------+
- | APA | [7-4] | y |
- +------------------------------+---------+---------+
- | DPB | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | LS64 | [63-60] |
+ +------------------------------+---------+
+ | I8MM | [55-52] |
+ +------------------------------+---------+
+ | DGH | [51-48] |
+ +------------------------------+---------+
+ | BF16 | [47-44] |
+ +------------------------------+---------+
+ | SB | [39-36] |
+ +------------------------------+---------+
+ | FRINTTS | [35-32] |
+ +------------------------------+---------+
+ | GPI | [31-28] |
+ +------------------------------+---------+
+ | GPA | [27-24] |
+ +------------------------------+---------+
+ | LRCPC | [23-20] |
+ +------------------------------+---------+
+ | FCMA | [19-16] |
+ +------------------------------+---------+
+ | JSCVT | [15-12] |
+ +------------------------------+---------+
+ | API | [11-8] |
+ +------------------------------+---------+
+ | APA | [7-4] |
+ +------------------------------+---------+
+ | DPB | [3-0] |
+ +------------------------------+---------+
ID_AA64ISAR2_EL1 - Instruction set attribute register 2
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | LUT | [59-56] | y |
- +------------------------------+---------+---------+
- | CSSC | [55-52] | y |
- +------------------------------+---------+---------+
- | RPRFM | [51-48] | y |
- +------------------------------+---------+---------+
- | BC | [23-20] | y |
- +------------------------------+---------+---------+
- | MOPS | [19-16] | y |
- +------------------------------+---------+---------+
- | APA3 | [15-12] | y |
- +------------------------------+---------+---------+
- | GPA3 | [11-8] | y |
- +------------------------------+---------+---------+
- | RPRES | [7-4] | y |
- +------------------------------+---------+---------+
- | WFXT | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | LUT | [59-56] |
+ +------------------------------+---------+
+ | CSSC | [55-52] |
+ +------------------------------+---------+
+ | RPRFM | [51-48] |
+ +------------------------------+---------+
+ | BC | [23-20] |
+ +------------------------------+---------+
+ | MOPS | [19-16] |
+ +------------------------------+---------+
+ | APA3 | [15-12] |
+ +------------------------------+---------+
+ | GPA3 | [11-8] |
+ +------------------------------+---------+
+ | RPRES | [7-4] |
+ +------------------------------+---------+
+ | WFXT | [3-0] |
+ +------------------------------+---------+
ID_AA64ISAR3_EL1 - Instruction set attribute register 3
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | FPRCVT | [31-28] | y |
- +------------------------------+---------+---------+
- | LSFE | [19-16] | y |
- +------------------------------+---------+---------+
- | FAMINMAX | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | FPRCVT | [31-28] |
+ +------------------------------+---------+
+ | LSFE | [19-16] |
+ +------------------------------+---------+
+ | FAMINMAX | [7-4] |
+ +------------------------------+---------+
ID_AA64MMFR0_EL1 - Memory model feature register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | ECV | [63-60] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | ECV | [63-60] |
+ +------------------------------+---------+
ID_AA64MMFR1_EL1 - Memory model feature register 1
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | AFP | [47-44] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | AFP | [47-44] |
+ +------------------------------+---------+
ID_AA64MMFR2_EL1 - Memory model feature register 2
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | AT | [35-32] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | AT | [35-32] |
+ +------------------------------+---------+
ID_AA64MMFR3_EL1 - Memory model feature register 3
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | S1POE | [19-16] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | S1POE | [19-16] |
+ +------------------------------+---------+
ID_AA64PFR0_EL1 - Processor Feature Register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | DIT | [51-48] | y |
- +------------------------------+---------+---------+
- | MPAM | [43-40] | n |
- +------------------------------+---------+---------+
- | SVE | [35-32] | y |
- +------------------------------+---------+---------+
- | GIC | [27-24] | n |
- +------------------------------+---------+---------+
- | AdvSIMD | [23-20] | y |
- +------------------------------+---------+---------+
- | FP | [19-16] | y |
- +------------------------------+---------+---------+
- | EL3 | [15-12] | n |
- +------------------------------+---------+---------+
- | EL2 | [11-8] | n |
- +------------------------------+---------+---------+
- | EL1 | [7-4] | n |
- +------------------------------+---------+---------+
- | EL0 | [3-0] | n |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | DIT | [51-48] |
+ +------------------------------+---------+
+ | SVE | [35-32] |
+ +------------------------------+---------+
+ | AdvSIMD | [23-20] |
+ +------------------------------+---------+
+ | FP | [19-16] |
+ +------------------------------+---------+
ID_AA64PFR1_EL1 - Processor Feature Register 1
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | GCS | [47-44] | y |
- +------------------------------+---------+---------+
- | SME | [27-24] | y |
- +------------------------------+---------+---------+
- | MTE | [11-8] | y |
- +------------------------------+---------+---------+
- | SSBS | [7-4] | y |
- +------------------------------+---------+---------+
- | BT | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | GCS | [47-44] |
+ +------------------------------+---------+
+ | SME | [27-24] |
+ +------------------------------+---------+
+ | MTE | [11-8] |
+ +------------------------------+---------+
+ | SSBS | [7-4] |
+ +------------------------------+---------+
+ | BT | [3-0] |
+ +------------------------------+---------+
ID_AA64PFR2_EL1 - Processor Feature Register 2
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | FPMR | [35-32] | y |
- +------------------------------+---------+---------+
- | MTEFAR | [11-8] | y |
- +------------------------------+---------+---------+
- | MTESTOREONLY | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | FPMR | [35-32] |
+ +------------------------------+---------+
+ | MTEFAR | [11-8] |
+ +------------------------------+---------+
+ | MTESTOREONLY | [7-4] |
+ +------------------------------+---------+
ID_AA64SMFR0_EL1 - SME feature ID register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | FA64 | [63] | y |
- +------------------------------+---------+---------+
- | LUT6 | [61] | y |
- +------------------------------+---------+---------+
- | LUTv2 | [60] | y |
- +------------------------------+---------+---------+
- | SMEver | [59-56] | y |
- +------------------------------+---------+---------+
- | I16I64 | [55-52] | y |
- +------------------------------+---------+---------+
- | F64F64 | [48] | y |
- +------------------------------+---------+---------+
- | I16I32 | [47-44] | y |
- +------------------------------+---------+---------+
- | B16B16 | [43] | y |
- +------------------------------+---------+---------+
- | F16F16 | [42] | y |
- +------------------------------+---------+---------+
- | F8F16 | [41] | y |
- +------------------------------+---------+---------+
- | F8F32 | [40] | y |
- +------------------------------+---------+---------+
- | I8I32 | [39-36] | y |
- +------------------------------+---------+---------+
- | F16F32 | [35] | y |
- +------------------------------+---------+---------+
- | B16F32 | [34] | y |
- +------------------------------+---------+---------+
- | BI32I32 | [33] | y |
- +------------------------------+---------+---------+
- | F32F32 | [32] | y |
- +------------------------------+---------+---------+
- | SF8FMA | [30] | y |
- +------------------------------+---------+---------+
- | SF8DP4 | [29] | y |
- +------------------------------+---------+---------+
- | SF8DP2 | [28] | y |
- +------------------------------+---------+---------+
- | SBitPerm | [25] | y |
- +------------------------------+---------+---------+
- | AES | [24] | y |
- +------------------------------+---------+---------+
- | SFEXPA | [23] | y |
- +------------------------------+---------+---------+
- | STMOP | [16] | y |
- +------------------------------+---------+---------+
- | SMOP4 | [0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | FA64 | [63] |
+ +------------------------------+---------+
+ | LUT6 | [61] |
+ +------------------------------+---------+
+ | LUTv2 | [60] |
+ +------------------------------+---------+
+ | SMEver | [59-56] |
+ +------------------------------+---------+
+ | I16I64 | [55-52] |
+ +------------------------------+---------+
+ | F64F64 | [48] |
+ +------------------------------+---------+
+ | I16I32 | [47-44] |
+ +------------------------------+---------+
+ | B16B16 | [43] |
+ +------------------------------+---------+
+ | F16F16 | [42] |
+ +------------------------------+---------+
+ | F8F16 | [41] |
+ +------------------------------+---------+
+ | F8F32 | [40] |
+ +------------------------------+---------+
+ | I8I32 | [39-36] |
+ +------------------------------+---------+
+ | F16F32 | [35] |
+ +------------------------------+---------+
+ | B16F32 | [34] |
+ +------------------------------+---------+
+ | BI32I32 | [33] |
+ +------------------------------+---------+
+ | F32F32 | [32] |
+ +------------------------------+---------+
+ | SF8FMA | [30] |
+ +------------------------------+---------+
+ | SF8DP4 | [29] |
+ +------------------------------+---------+
+ | SF8DP2 | [28] |
+ +------------------------------+---------+
+ | SBitPerm | [25] |
+ +------------------------------+---------+
+ | AES | [24] |
+ +------------------------------+---------+
+ | SFEXPA | [23] |
+ +------------------------------+---------+
+ | STMOP | [16] |
+ +------------------------------+---------+
+ | SMOP4 | [0] |
+ +------------------------------+---------+
ID_AA64ZFR0_EL1 - SVE feature ID register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | F64MM | [59-56] | y |
- +------------------------------+---------+---------+
- | F32MM | [55-52] | y |
- +------------------------------+---------+---------+
- | F16MM | [51-48] | y |
- +------------------------------+---------+---------+
- | I8MM | [47-44] | y |
- +------------------------------+---------+---------+
- | SM4 | [43-40] | y |
- +------------------------------+---------+---------+
- | SHA3 | [35-32] | y |
- +------------------------------+---------+---------+
- | B16B16 | [27-24] | y |
- +------------------------------+---------+---------+
- | BF16 | [23-20] | y |
- +------------------------------+---------+---------+
- | BitPerm | [19-16] | y |
- +------------------------------+---------+---------+
- | EltPerm | [15-12] | y |
- +------------------------------+---------+---------+
- | AES | [7-4] | y |
- +------------------------------+---------+---------+
- | SVEVer | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | F64MM | [59-56] |
+ +------------------------------+---------+
+ | F32MM | [55-52] |
+ +------------------------------+---------+
+ | F16MM | [51-48] |
+ +------------------------------+---------+
+ | I8MM | [47-44] |
+ +------------------------------+---------+
+ | SM4 | [43-40] |
+ +------------------------------+---------+
+ | SHA3 | [35-32] |
+ +------------------------------+---------+
+ | B16B16 | [27-24] |
+ +------------------------------+---------+
+ | BF16 | [23-20] |
+ +------------------------------+---------+
+ | BitPerm | [19-16] |
+ +------------------------------+---------+
+ | EltPerm | [15-12] |
+ +------------------------------+---------+
+ | AES | [7-4] |
+ +------------------------------+---------+
+ | SVEVer | [3-0] |
+ +------------------------------+---------+
ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | CRC32 | [19-16] | y |
- +------------------------------+---------+---------+
- | SHA2 | [15-12] | y |
- +------------------------------+---------+---------+
- | SHA1 | [11-8] | y |
- +------------------------------+---------+---------+
- | AES | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | CRC32 | [19-16] |
+ +------------------------------+---------+
+ | SHA2 | [15-12] |
+ +------------------------------+---------+
+ | SHA1 | [11-8] |
+ +------------------------------+---------+
+ | AES | [7-4] |
+ +------------------------------+---------+
ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | I8MM | [27-24] | y |
- +------------------------------+---------+---------+
- | BF16 | [23-20] | y |
- +------------------------------+---------+---------+
- | SB | [15-12] | y |
- +------------------------------+---------+---------+
- | FHM | [11-8] | y |
- +------------------------------+---------+---------+
- | DP | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | I8MM | [27-24] |
+ +------------------------------+---------+
+ | BF16 | [23-20] |
+ +------------------------------+---------+
+ | SB | [15-12] |
+ +------------------------------+---------+
+ | FHM | [11-8] |
+ +------------------------------+---------+
+ | DP | [7-4] |
+ +------------------------------+---------+
ID_PFR2_EL1 - AArch32 Processor Feature Register 2
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | SSBS | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | SSBS | [7-4] |
+ +------------------------------+---------+
MIDR_EL1 - Main ID Register
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | Implementer | [31-24] | y |
- +------------------------------+---------+---------+
- | Variant | [23-20] | y |
- +------------------------------+---------+---------+
- | Architecture | [19-16] | y |
- +------------------------------+---------+---------+
- | PartNum | [15-4] | y |
- +------------------------------+---------+---------+
- | Revision | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | Implementer | [31-24] |
+ +------------------------------+---------+
+ | Variant | [23-20] |
+ +------------------------------+---------+
+ | Architecture | [19-16] |
+ +------------------------------+---------+
+ | PartNum | [15-4] |
+ +------------------------------+---------+
+ | Revision | [3-0] |
+ +------------------------------+---------+
NOTE: The 'visible' fields of MIDR_EL1 will contain the value
as available on the CPU where it is fetched and is not a system
@@ -471,29 +459,29 @@ infrastructure:
MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | FPDP | [11-8] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | FPDP | [11-8] |
+ +------------------------------+---------+
MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | SIMDFMAC | [31-28] | y |
- +------------------------------+---------+---------+
- | FPHP | [27-24] | y |
- +------------------------------+---------+---------+
- | SIMDHP | [23-20] | y |
- +------------------------------+---------+---------+
- | SIMDSP | [19-16] | y |
- +------------------------------+---------+---------+
- | SIMDInt | [15-12] | y |
- +------------------------------+---------+---------+
- | SIMDLS | [11-8] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | SIMDFMAC | [31-28] |
+ +------------------------------+---------+
+ | FPHP | [27-24] |
+ +------------------------------+---------+
+ | SIMDHP | [23-20] |
+ +------------------------------+---------+
+ | SIMDSP | [19-16] |
+ +------------------------------+---------+
+ | SIMDInt | [15-12] |
+ +------------------------------+---------+
+ | SIMDLS | [11-8] |
+ +------------------------------+---------+
Appendix I: Example
--
2.47.3
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2026-07-02 19:11 [PATCH v2 0/4] arm64: Fixes and cleanups for cpu-feature-registers.rst Mark Brown
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