[PATCH v2 0/3] riscv: mm: Some optimizations for tlb flush

[Xu Lu <luxu.kernel@bytedance.com>]

Some optimizations for tlb flush on RISC-V smp:
1. Apply Svinval in update_mmu_cache() to avoid flushing irrelevant tlb
entries.
2. Clear bit of current cpu in mm_cpumask after local_flush_tlb_all_asid()
to avoid potential IPIs in the future.

Some false positive spacing error happens during patch checking. Thus I
CCed maintainers of checkpatch.pl as well.

Changes in V2:
1. Split the modification on update_mmu_cache() into two commits. Thanks
to Paul.
2. Fix address errors in the svinval processing path in V1. Thanks to
Klara.

Xu Lu (3):
  riscv: mm: Use ASID in update_mmu_cache()
  riscv: mm: Apply Svinval in update_mmu_cache()
  riscv: mm: Clear cpu in mm_cpumask after local_flush_tlb_all_asid

 arch/riscv/include/asm/pgtable.h  | 12 +++++-
 arch/riscv/include/asm/tlbflush.h | 23 +++++++++++
 arch/riscv/mm/tlbflush.c          | 64 ++++++++++++-------------------
 3 files changed, 59 insertions(+), 40 deletions(-)

-- 
2.39.5