Re: [PATCH v2 2/3] riscv: mm: Apply Svinval in update_mmu_cache()

[Klara Modin <klarasmodin@gmail.com>]

On 2026-07-17 09:08:59 +0200, Marek Szyprowski wrote:
> On 15.07.2026 20:22, Klara Modin wrote:
> > On 2026-07-15 21:20:08 +0800, Xu Lu wrote:
> >> Use Svinval in update_mmu_cache_range() when the extension is available.
> >>
> >> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> > This version works fine for me.
> 
> Lucky You! Here BPiF3 gets frozen once userspace has started.

The old version of patch 1 of the series was used when the series was
applied for next, whereas I reverted the old series and applied the
entirety of the second version when I tested. I commented this on patch
1.

Regards,
Klara Modin

> 
> 
> > Thanks,
> > Tested-by: Klara Modin <klarasmodin@gmail.com>
> >
> >> ---
> >>  arch/riscv/include/asm/pgtable.h  |  8 ++++++++
> >>  arch/riscv/include/asm/tlbflush.h | 18 ++++++++++++++++++
> >>  arch/riscv/mm/tlbflush.c          | 18 ------------------
> >>  3 files changed, 26 insertions(+), 18 deletions(-)
> >>
> >> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> >> index 9926556099ae..823805cc465a 100644
> >> --- a/arch/riscv/include/asm/pgtable.h
> >> +++ b/arch/riscv/include/asm/pgtable.h
> >> @@ -578,6 +578,14 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
> >>  	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC))
> >>  		return;
> >>  
> >> +	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)) {
> >> +		local_sfence_w_inval();
> >> +		while (nr--)
> >> +			local_sinval_vma(address + nr * PAGE_SIZE, asid);
> 
> 'asid' is not initialized here. The following fixup is needed:
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 3c17ad0786ab..e283649e1dee 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -570,32 +570,32 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
>         /*
>          * Svvptc guarantees that the new valid pte will be visible within
>          * a bounded timeframe, so when the uarch does not cache invalid
>          * entries, we don't have to do anything.
>          */
>         if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC))
>                 return;
> 
> +       asid = get_mm_asid(vma->vm_mm);
>         if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)) {
>                 local_sfence_w_inval();
>                 while (nr--)
>                         local_sinval_vma(address + nr * PAGE_SIZE, asid);
>                 local_sfence_inval_ir();
>                 return;
>         }
> 
>         /*
>          * The kernel assumes that TLBs don't cache invalid entries, but
>          * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a
>          * cache flush; it is necessary even after writing invalid entries.
>          * Relying on flush_tlb_fix_spurious_fault would suffice, but
>          * the extra traps reduce performance.  So, eagerly SFENCE.VMA.
>          */
> -       asid = get_mm_asid(vma->vm_mm);
>         while (nr--)
>                 local_flush_tlb_page_asid(address + nr * PAGE_SIZE, asid);
>  }
> 
>  #define update_mmu_cache(vma, addr, ptep) \
>         update_mmu_cache_range(NULL, vma, addr, ptep, 1)
> 
>  #define update_mmu_tlb_range(vma, addr, ptep, nr) \
> 
> 
> 
> >> +		local_sfence_inval_ir();
> >> +		return;
> >> +	}
> >> +
> >>  	/*
> >>  	 * The kernel assumes that TLBs don't cache invalid entries, but
> >>  	 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a
> >> diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
> >> index 7c2cd5cc92d3..9636d07fe9ee 100644
> >> --- a/arch/riscv/include/asm/tlbflush.h
> >> +++ b/arch/riscv/include/asm/tlbflush.h
> >> @@ -20,6 +20,24 @@ static inline unsigned long get_mm_asid(struct mm_struct *mm)
> >>  	return mm ? cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID;
> >>  }
> >>  
> >> +static inline void local_sfence_inval_ir(void)
> >> +{
> >> +	asm volatile(SFENCE_INVAL_IR() ::: "memory");
> >> +}
> >> +
> >> +static inline void local_sfence_w_inval(void)
> >> +{
> >> +	asm volatile(SFENCE_W_INVAL() ::: "memory");
> >> +}
> >> +
> >> +static inline void local_sinval_vma(unsigned long vma, unsigned long asid)
> >> +{
> >> +	if (asid != FLUSH_TLB_NO_ASID)
> >> +		asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory");
> >> +	else
> >> +		asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory");
> >> +}
> >> +
> >>  static inline void local_flush_tlb_all(void)
> >>  {
> >>  	__asm__ __volatile__ ("sfence.vma" : : : "memory");
> >> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> >> index 73c226f719c7..962db300a166 100644
> >> --- a/arch/riscv/mm/tlbflush.c
> >> +++ b/arch/riscv/mm/tlbflush.c
> >> @@ -11,24 +11,6 @@
> >>  
> >>  #define has_svinval()	riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)
> >>  
> >> -static inline void local_sfence_inval_ir(void)
> >> -{
> >> -	asm volatile(SFENCE_INVAL_IR() ::: "memory");
> >> -}
> >> -
> >> -static inline void local_sfence_w_inval(void)
> >> -{
> >> -	asm volatile(SFENCE_W_INVAL() ::: "memory");
> >> -}
> >> -
> >> -static inline void local_sinval_vma(unsigned long vma, unsigned long asid)
> >> -{
> >> -	if (asid != FLUSH_TLB_NO_ASID)
> >> -		asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory");
> >> -	else
> >> -		asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory");
> >> -}
> >> -
> >>  /*
> >>   * Flush entire TLB if number of entries to be flushed is greater
> >>   * than the threshold below.
> >> -- 
> >> 2.39.5
> >>
> Best regards
> -- 
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
>