[PATCH RFC 0/2] irqchip/ls-scfg-msi: add multi-MSI support

[PATCH RFC 0/2] irqchip/ls-scfg-msi: add multi-MSI support

[Alexander Wilhelm]

This series enables multi-MSI (nr_irqs > 1) allocation on the Layerscape
SCFG MSI controller so PCI endpoints that request contiguous MSI vector
blocks (for example ath12k, which asks for 16 vectors: 3 MHI + 5 CE + 8 DP)
no longer fall back to single-MSI operation with all interrupts multiplexed
onto one CPU.

The first patch is a preparation refactor: switch the hwirq bookkeeping
from find_first_zero_bit() / __set_bit() to bitmap_find_free_region() /
bitmap_release_region(), release the region on iommu_dma_prepare_msi()
error, and loop irq_domain_set_info() over nr_irqs. For the current
single-MSI case (order 0) this is functionally equivalent; the only
externally visible change is -ENOMEM instead of -ENOSPC on exhaustion.

The second patch enables MSI_FLAG_MULTI_PCI_MSI on the parent domain, drops
the WARN_ON(nr_irqs != 1) guard, and statically pins each MSIR's chained
parent IRQ to its matching CPU in no-affinity mode. That pinning is
required because affinity mode only releases every (1 << ibs_shift)-th
hwirq and cannot satisfy aligned power-of-two allocations of size > 1;
users of multi-MSI must therefore boot with lsmsi=no-affinity.

Signed-off-by: Alexander Wilhelm <alexander.wilhelm@westermo.com>
---
Alexander Wilhelm (2):
      irqchip/ls-scfg-msi: refactor allocation to bitmap_find_free_region()
      irqchip/ls-scfg-msi: enable multi-MSI allocation

 drivers/irqchip/irq-ls-scfg-msi.c | 45 +++++++++++++++++++++++----------------
 1 file changed, 27 insertions(+), 18 deletions(-)
---
base-commit: 37e2f878a7a660a216cc7a60459995fefd150f25
change-id: 20260716-irqchip-ls-scfg-msi-add-multi-msi-support-5e7538460704

Best regards,
-- 
Alexander Wilhelm <alexander.wilhelm@westermo.com>

[PATCH RFC 1/2] irqchip/ls-scfg-msi: refactor allocation to bitmap_find_free_region()

[Alexander Wilhelm]

Replace the manual find_first_zero_bit()/__set_bit() pair with
bitmap_find_free_region(), and __clear_bit() with bitmap_release_region().

For the current single-MSI case (guarded by WARN_ON(nr_irqs != 1)) with
order 0 this is functionally equivalent: bitmap_find_free_region() walks
the bitmap in single-bit units and internally does the test-and-set
atomically under the same lock. On failure it returns -ENOMEM which is now
propagated directly, replacing the previous -ENOSPC.

While at it, release the region on iommu_dma_prepare_msi() failure instead
of leaking the allocated bit, loop over nr_irqs when calling
irq_domain_set_info(), and range-check pos + nr_irqs in the free path. All
three are no-ops for nr_irqs = 1 but prepare the driver for a subsequent
MSI_FLAG_MULTI_PCI_MSI enable without further changes to the allocation
bookkeeping.

Assisted-by: Copilot:claude-opus-4.7
Signed-off-by: Alexander Wilhelm <alexander.wilhelm@westermo.com>
---
 drivers/irqchip/irq-ls-scfg-msi.c | 36 +++++++++++++++++++++---------------
 1 file changed, 21 insertions(+), 15 deletions(-)

diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index 4910f364e568..bd5833ef621a 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -141,28 +141,32 @@ static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
 {
 	msi_alloc_info_t *info = args;
 	struct ls_scfg_msi *msi_data = domain->host_data;
-	int pos, err = 0;
+	int order = get_count_order(nr_irqs);
+	int pos, err;
+	unsigned int i;
 
 	WARN_ON(nr_irqs != 1);
 
 	spin_lock(&msi_data->lock);
-	pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
-	if (pos < msi_data->irqs_num)
-		__set_bit(pos, msi_data->used);
-	else
-		err = -ENOSPC;
+	pos = bitmap_find_free_region(msi_data->used, msi_data->irqs_num,
+				      order);
 	spin_unlock(&msi_data->lock);
 
-	if (err)
-		return err;
+	if (pos < 0)
+		return pos;
 
 	err = iommu_dma_prepare_msi(info->desc, msi_data->msiir_addr);
-	if (err)
+	if (err) {
+		spin_lock(&msi_data->lock);
+		bitmap_release_region(msi_data->used, pos, order);
+		spin_unlock(&msi_data->lock);
 		return err;
+	}
 
-	irq_domain_set_info(domain, virq, pos,
-			    &ls_scfg_msi_parent_chip, msi_data,
-			    handle_simple_irq, NULL, NULL);
+	for (i = 0; i < nr_irqs; i++)
+		irq_domain_set_info(domain, virq + i, pos + i,
+				    &ls_scfg_msi_parent_chip, msi_data,
+				    handle_simple_irq, NULL, NULL);
 
 	return 0;
 }
@@ -172,16 +176,18 @@ static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
 {
 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 	struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d);
+	int order = get_count_order(nr_irqs);
 	int pos;
 
 	pos = d->hwirq;
-	if (pos < 0 || pos >= msi_data->irqs_num) {
-		pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
+	if (pos < 0 || pos + nr_irqs > msi_data->irqs_num) {
+		pr_err("failed to teardown msi. Invalid hwirq %d nr %u\n",
+		       pos, nr_irqs);
 		return;
 	}
 
 	spin_lock(&msi_data->lock);
-	__clear_bit(pos, msi_data->used);
+	bitmap_release_region(msi_data->used, pos, order);
 	spin_unlock(&msi_data->lock);
 }
 

-- 
2.43.0

[PATCH RFC 2/2] irqchip/ls-scfg-msi: enable multi-MSI allocation

[Alexander Wilhelm]

Add MSI_FLAG_MULTI_PCI_MSI to the parent domain's supported flags so PCI
devices can request more than one contiguous MSI vector. The previous
refactor to bitmap_find_free_region() already handles arbitrary
power-of-two orders, so drop the WARN_ON(nr_irqs != 1) guard.

In practice, multi-MSI requires the 'no-affinity' MSIR routing, because
affinity mode only releases every (1 << ibs_shift)-th hwirq and therefore
cannot satisfy aligned power-of-two blocks larger than one bit. Statically
pin each MSIR's chained parent IRQ to its matching CPU in that mode: the
low ibs_shift bits of the hwirq then select both the MSIR and the target
CPU, giving each MSI vector a deterministic target CPU without runtime
migration.

Assisted-by: Copilot:claude-opus-4.7
Signed-off-by: Alexander Wilhelm <alexander.wilhelm@westermo.com>
---
 drivers/irqchip/irq-ls-scfg-msi.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index bd5833ef621a..a9660bbcdf7f 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -60,6 +60,7 @@ struct ls_scfg_msi {
 #define MPIC_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
 				 MSI_FLAG_USE_DEF_CHIP_OPS)
 #define MPIC_MSI_FLAGS_SUPPORTED (MSI_FLAG_PCI_MSIX       | \
+				  MSI_FLAG_MULTI_PCI_MSI  | \
 				  MSI_GENERIC_FLAGS_MASK)
 
 static const struct msi_parent_ops ls_scfg_msi_parent_ops = {
@@ -145,8 +146,6 @@ static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
 	int pos, err;
 	unsigned int i;
 
-	WARN_ON(nr_irqs != 1);
-
 	spin_lock(&msi_data->lock);
 	pos = bitmap_find_free_region(msi_data->used, msi_data->irqs_num,
 				      order);
@@ -271,8 +270,12 @@ static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
 		/* Associate MSIR interrupt to the cpu */
 		irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
 		msir->srs = 0; /* This value is determined by the CPU */
-	} else
+	} else {
 		msir->srs = index;
+		/* Statically pin each MSIR to its matching CPU */
+		if (index < num_possible_cpus())
+			irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
+	}
 
 	/* Release the hwirqs corresponding to this MSIR */
 	if (!msi_affinity_flag || msir->index == 0) {

-- 
2.43.0