From: Mark Brown <broonie@kernel.org>
To: Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Oliver Upton <oupton@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
Mark Rutland <mark.rutland@arm.com>,
Ben Horgan <ben.horgan@arm.com>,
Jean-Philippe Brucker <jpb@kernel.org>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Peter Maydell <peter.maydell@linaro.org>,
Eric Auger <eric.auger@redhat.com>,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v13 26/32] KVM: arm64: Handle SME exceptions
Date: Mon, 20 Jul 2026 00:07:53 +0100 [thread overview]
Message-ID: <20260720-kvm-arm64-sme-v13-26-d9abd3ffa245@kernel.org> (raw)
In-Reply-To: <20260720-kvm-arm64-sme-v13-0-d9abd3ffa245@kernel.org>
The access control for SME follows the same structure as for the base FP
and SVE extensions, with control being via CPACR_ELx.SMEN and CPTR_EL2.TSM
mirroring the equivalent FPSIMD and SVE controls in those registers. Add
handling for these controls and exceptions mirroring the existing handling
for FPSIMD and SVE, plus handling for emulation of SMCR_EL2.EZT0.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/kvm/handle_exit.c | 19 +++++++++++++++++++
arch/arm64/kvm/hyp/include/hyp/switch.h | 11 ++++++-----
arch/arm64/kvm/hyp/nvhe/switch.c | 2 ++
arch/arm64/kvm/hyp/vhe/switch.c | 1 +
4 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index f674cd25d894..24d54e977a31 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -233,6 +233,24 @@ static int handle_sve(struct kvm_vcpu *vcpu)
return 1;
}
+static int handle_sme(struct kvm_vcpu *vcpu)
+{
+ u64 esr = kvm_vcpu_get_esr(vcpu);
+
+ if (guest_hyp_sme_traps_enabled(vcpu))
+ return kvm_inject_nested_sync(vcpu, esr);
+
+ /* Reinject SME EZT0 traps that were enabled by the guest. */
+ if (vcpu_has_sme2(vcpu) &&
+ ESR_ELx_EC(esr) == ESR_ELx_EC_SME &&
+ ESR_ELx_SME_ISS_SMTC(esr) == ESR_ELx_SME_ISS_SMTC_ZT_DISABLED &&
+ !(__vcpu_sys_reg(vcpu, SMCR_EL2) & SMCR_ELx_EZT0))
+ return kvm_inject_nested_sync(vcpu, esr);
+
+ kvm_inject_undefined(vcpu);
+ return 1;
+}
+
/*
* Two possibilities to handle a trapping ptrauth instruction:
*
@@ -386,6 +404,7 @@ static exit_handle_fn arm_exit_handlers[] = {
[ESR_ELx_EC_SVC64] = handle_svc,
[ESR_ELx_EC_SYS64] = kvm_handle_sys_reg,
[ESR_ELx_EC_SVE] = handle_sve,
+ [ESR_ELx_EC_SME] = handle_sme,
[ESR_ELx_EC_ERET] = kvm_handle_eret,
[ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort,
[ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort,
diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 2eabffb640e9..5987b550ad34 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -67,11 +67,8 @@ static inline void __activate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
{
u64 val = CPTR_NVHE_EL2_RES1 | CPTR_EL2_TAM | CPTR_EL2_TTA;
- /*
- * Always trap SME since it's not supported in KVM.
- * TSM is RES1 if SME isn't implemented.
- */
- val |= CPTR_EL2_TSM;
+ if (!vcpu_has_sme(vcpu) || !guest_owns_fp_regs())
+ val |= CPTR_EL2_TSM;
if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
val |= CPTR_EL2_TZ;
@@ -99,6 +96,8 @@ static inline void __activate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
val |= CPACR_EL1_FPEN;
if (vcpu_has_sve(vcpu))
val |= CPACR_EL1_ZEN;
+ if (vcpu_has_sme(vcpu))
+ val |= CPACR_EL1_SMEN;
}
if (!vcpu_has_nv(vcpu))
@@ -140,6 +139,8 @@ static inline void __activate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
val &= ~CPACR_EL1_FPEN;
if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0)))
val &= ~CPACR_EL1_ZEN;
+ if (!(SYS_FIELD_GET(CPACR_EL1, SMEN, cptr) & BIT(0)))
+ val &= ~CPACR_EL1_SMEN;
if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1POE, IMP))
val |= cptr & CPACR_EL1_E0POE;
diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c
index 7318e3e6a5f3..2d5029dbfb00 100644
--- a/arch/arm64/kvm/hyp/nvhe/switch.c
+++ b/arch/arm64/kvm/hyp/nvhe/switch.c
@@ -196,6 +196,7 @@ static const exit_handler_fn hyp_exit_handlers[] = {
[ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
[ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg,
[ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
+ [ESR_ELx_EC_SME] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
[ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
@@ -208,6 +209,7 @@ static const exit_handler_fn pvm_exit_handlers[] = {
[ESR_ELx_EC_HVC64] = kvm_handle_pvm_hvc64,
[ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64,
[ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted,
+ [ESR_ELx_EC_SME] = kvm_handle_pvm_restricted,
[ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
[ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
index 625fe81a20b1..2931a1a1fe90 100644
--- a/arch/arm64/kvm/hyp/vhe/switch.c
+++ b/arch/arm64/kvm/hyp/vhe/switch.c
@@ -495,6 +495,7 @@ static const exit_handler_fn hyp_exit_handlers[] = {
[0 ... ESR_ELx_EC_MAX] = NULL,
[ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
[ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg_vhe,
+ [ESR_ELx_EC_SME] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
--
2.47.3
next prev parent reply other threads:[~2026-07-19 23:11 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-19 23:07 [PATCH v13 00/32] KVM: arm64: Implement support for SME Mark Brown
2026-07-19 23:07 ` [PATCH v13 01/32] arm64/sysreg: Define full value read/modify/write helpers Mark Brown
2026-07-19 23:07 ` [PATCH v13 02/32] arm64/fpsimd: Ensure all of ZCR_EL1 is initialised from idle Mark Brown
2026-07-23 12:58 ` Mark Rutland
2026-07-24 15:16 ` Mark Rutland
2026-07-19 23:07 ` [PATCH v13 03/32] arm64/fpsimd: Configure all ZCR/SMCR bits when loading task state Mark Brown
2026-07-19 23:07 ` [PATCH v13 04/32] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2026-07-19 23:07 ` [PATCH v13 05/32] arm64/sve: Factor virtualizable VL discovery out of SVE specific code Mark Brown
2026-07-19 23:07 ` [PATCH v13 06/32] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2026-07-19 23:07 ` [PATCH v13 07/32] KVM: arm64: Remove bitrotted comment on handle_sve() Mark Brown
2026-07-19 23:07 ` [PATCH v13 08/32] KVM: arm64: Handle FEAT_IDST for guest accesses to hidden registers Mark Brown
2026-07-19 23:07 ` [PATCH v13 09/32] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2026-07-19 23:07 ` [PATCH v13 10/32] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2026-07-19 23:07 ` [PATCH v13 11/32] KVM: arm64: Remove special case for FP state loading from ZCR_EL2 traps Mark Brown
2026-07-19 23:07 ` [PATCH v13 12/32] KVM: arm64: Define internal features for SME Mark Brown
2026-07-19 23:07 ` [PATCH v13 13/32] KVM: arm64: Rename sve_state_reg_region Mark Brown
2026-07-19 23:07 ` [PATCH v13 14/32] KVM: arm64: Store vector lengths in an array Mark Brown
2026-07-19 23:07 ` [PATCH v13 15/32] KVM: arm64: Factor SVE code out of fpsimd_lazy_switch_to_host() Mark Brown
2026-07-19 23:07 ` [PATCH v13 16/32] KVM: arm64: Document the KVM ABI for SME Mark Brown
2026-07-19 23:07 ` [PATCH v13 17/32] KVM: arm64: Implement SME vector length configuration Mark Brown
2026-07-19 23:07 ` [PATCH v13 18/32] KVM: arm64: Support SME control registers Mark Brown
2026-07-19 23:07 ` [PATCH v13 19/32] KVM: arm64: Support TPIDR2_EL0 Mark Brown
2026-07-19 23:07 ` [PATCH v13 20/32] KVM: arm64: Support SME identification registers for guests Mark Brown
2026-07-19 23:07 ` [PATCH v13 21/32] KVM: arm64: Support SME priority registers Mark Brown
2026-07-19 23:07 ` [PATCH v13 22/32] KVM: arm64: Support userspace access to streaming mode Z and P registers Mark Brown
2026-07-19 23:07 ` [PATCH v13 23/32] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Mark Brown
2026-07-19 23:07 ` [PATCH v13 24/32] KVM: arm64: Expose SME specific state to userspace Mark Brown
2026-07-19 23:07 ` [PATCH v13 25/32] KVM: arm64: Context switch SME state for guests Mark Brown
2026-07-19 23:07 ` Mark Brown [this message]
2026-07-19 23:07 ` [PATCH v13 27/32] KVM: arm64: Expose SME to nested guests Mark Brown
2026-07-19 23:07 ` [PATCH v13 28/32] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2026-07-19 23:07 ` [PATCH v13 29/32] KVM: arm64: selftests: Remove spurious check for single bit safe values Mark Brown
2026-07-19 23:07 ` [PATCH v13 30/32] KVM: arm64: selftests: Skip impossible invalid value tests Mark Brown
2026-07-19 23:07 ` [PATCH v13 31/32] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2026-07-19 23:07 ` [PATCH v13 32/32] KVM: arm64: selftests: Add SME to set_id_regs test Mark Brown
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