[PATCH] irqchip/ast2700-intc: Disable all interrupt merge banks on probe

[PATCH] irqchip/ast2700-intc: Disable all interrupt merge banks on probe

[Michael Pesa]

The INTC0 interrupt-merge (INTM) space has 50 sources at 10 per bank, i.e.
INTC0_INTM_NUM / INTM_IRQS_PER_BANK = 5 banks. This is reflected everywhere
the banks are indexed: the aspeed_intc0_intm_routes[] table has 5 valid
entries, and the mask/unmask/eoi paths compute the bank as (hwirq -
INTM_BASE) / INTM_IRQS_PER_BANK, spanning banks 0-4.  However,
INTC0_INTM_BANK_NUM is hardcoded to 3, so aspeed_intc0_disable_intm()
only clears IER for banks 0-2 at probe. Banks 3 and 4 are left in whatever
state firmware configured, which can leave interrupts enabled before a
handler is installed.

Derive the bank count from the source count so the probe-time disable
covers every bank.

Fixes: 07825e41519a ("irqchip/ast2700-intc: Add AST2700-A2 support")
Signed-off-by: Michael Pesa <michael.pesa@icloud.com>
---

Notes:
    Tested with the ast2700-intc0 KUnit suite (9/9 passing) and boot-tested
    on QEMU 10.2's ast2700-evb model with the intc0/intc1 stack active:
    probe, hierarchical allocation and the merge-interrupt unmask paths
    behave identically with and without this change. Note that QEMU only
    implements the bank 0 INTM IER register, so the new probe-time writes to
    banks 3 and 4 are not observable under emulation; testing on hardware
    where firmware leaves the upper merge banks configured would be welcome.

 drivers/irqchip/irq-ast2700-intc0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-ast2700-intc0.c b/drivers/irqchip/irq-ast2700-intc0.c
index 14b8b88f1179..5db915570f48 100644
--- a/drivers/irqchip/irq-ast2700-intc0.c
+++ b/drivers/irqchip/irq-ast2700-intc0.c
@@ -48,9 +48,9 @@
 #define INTC0_INTMX_IER		0x1b00
 #define INTC0_INTMX_ISR		0x1b04
 #define INTC0_INTMX_BANK_SIZE	0x10
-#define INTC0_INTM_BANK_NUM	3
 #define INTC0_IRQS_PER_BANK	32
 #define INTM_IRQS_PER_BANK	10
+#define INTC0_INTM_BANK_NUM	(INTC0_INTM_NUM / INTM_IRQS_PER_BANK)
 #define INTC0_SEL_BASE			0x200
 #define INTC0_SEL_BANK_SIZE		0x4
 #define INTC0_SEL_ROUTE_SIZE	0x100

base-commit: 248951ddc14de84de3910f9b13f51491a8cd91df
-- 
2.55.0

[tip: irq/urgent] irqchip/ast2700-intc: Disable all interrupt merge banks on probe

[tip-bot2 for Michael Pesa]

The following commit has been merged into the irq/urgent branch of tip:

Commit-ID:     34b7e953d19a39515f8fc6c0820ebf243ea6b026
Gitweb:        https://git.kernel.org/tip/34b7e953d19a39515f8fc6c0820ebf243ea6b026
Author:        Michael Pesa <michael.pesa@icloud.com>
AuthorDate:    Tue, 21 Jul 2026 22:02:43 -07:00
Committer:     Thomas Gleixner <tglx@kernel.org>
CommitterDate: Thu, 20 Aug 2026 08:29:33 +02:00

irqchip/ast2700-intc: Disable all interrupt merge banks on probe

The INTC0 interrupt-merge (INTM) space has 50 sources at 10 per bank, i.e.
INTC0_INTM_NUM / INTM_IRQS_PER_BANK = 5 banks. This is reflected everywhere
the banks are indexed: the aspeed_intc0_intm_routes[] table has 5 valid
entries, and the mask/unmask/eoi paths compute the bank as (hwirq -
INTM_BASE) / INTM_IRQS_PER_BANK, spanning banks 0-4.

However, INTC0_INTM_BANK_NUM is hardcoded to 3, so
aspeed_intc0_disable_intm() only clears IER for banks 0-2 at probe. Banks 3
and 4 are left in whatever state the firmware configured them , which can
leave interrupts enabled before a handler is installed.

Derive the bank count from the source count so the probe-time disable
covers every bank.

Fixes: 07825e41519a ("irqchip/ast2700-intc: Add AST2700-A2 support")
Signed-off-by: Michael Pesa <michael.pesa@icloud.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260722050243.298355-1-michael.pesa@icloud.com
---
 drivers/irqchip/irq-ast2700-intc0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-ast2700-intc0.c b/drivers/irqchip/irq-ast2700-intc0.c
index c85b98a..1e375e9 100644
--- a/drivers/irqchip/irq-ast2700-intc0.c
+++ b/drivers/irqchip/irq-ast2700-intc0.c
@@ -48,9 +48,9 @@
 #define INTC0_INTMX_IER		0x1b00
 #define INTC0_INTMX_ISR		0x1b04
 #define INTC0_INTMX_BANK_SIZE	0x10
-#define INTC0_INTM_BANK_NUM	3
 #define INTC0_IRQS_PER_BANK	32
 #define INTM_IRQS_PER_BANK	10
+#define INTC0_INTM_BANK_NUM	(INTC0_INTM_NUM / INTM_IRQS_PER_BANK)
 #define INTC0_SEL_BASE			0x200
 #define INTC0_SEL_BANK_SIZE		0x4
 #define INTC0_SEL_ROUTE_SIZE	0x100