From: Davidlohr Bueso <dave@stgolabs.net>
To: dave.jiang@intel.com
Cc: jic23@kernel.org, alison.schofield@intel.com, icheng@nvidia.com,
benjamin.cheatham@amd.com, alucerop@amd.com,
dongjoo.seo1@samsung.com, dave@stgolabs.net,
linux-kernel@vger.kernel.org
Subject: [PATCH v6 5/9] cxl/hdm: Rename decoder coherency flags
Date: Mon, 27 Jul 2026 12:35:57 -0700 [thread overview]
Message-ID: <20260727193601.651871-6-dave@stgolabs.net> (raw)
In-Reply-To: <20260727193601.651871-1-dave@stgolabs.net>
Align with the ACPI CXL Window restriction naming and convert
CXL_DECODER_F_TYPE2/F_TYPE3 to F_DEVMEM/F_HOSTONLY. Type2 and
Type3 coherency models were named prior to Back-Invalidate.
Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
---
drivers/cxl/acpi.c | 8 ++++----
drivers/cxl/core/port.c | 12 ++++++------
drivers/cxl/cxl.h | 4 ++--
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index eceb8dd97df2..2c54f709c45d 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -143,9 +143,9 @@ static unsigned long cfmws_to_decoder_flags(int restrictions)
unsigned long flags = CXL_DECODER_F_ENABLE;
if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_DEVMEM)
- flags |= CXL_DECODER_F_TYPE2;
+ flags |= CXL_DECODER_F_DEVMEM;
if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYMEM)
- flags |= CXL_DECODER_F_TYPE3;
+ flags |= CXL_DECODER_F_HOSTONLY;
if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
flags |= CXL_DECODER_F_RAM;
if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
@@ -447,8 +447,8 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,
cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
/* host-only wins if firmware sets both coherency restrictions */
cxld->target_type = CXL_DECODER_HOSTONLYMEM;
- if (cxld->flags & CXL_DECODER_F_TYPE2) {
- if (cxld->flags & CXL_DECODER_F_TYPE3)
+ if (cxld->flags & CXL_DECODER_F_DEVMEM) {
+ if (cxld->flags & CXL_DECODER_F_HOSTONLY)
dev_dbg(dev, "CFMWS has both HDM-H and HDM-D\n");
else
cxld->target_type = CXL_DECODER_DEVMEM;
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 0bcb3ad7905c..4fce2188cd8c 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -128,8 +128,8 @@ static DEVICE_ATTR_RO(name)
CXL_DECODER_FLAG_ATTR(cap_pmem, CXL_DECODER_F_PMEM);
CXL_DECODER_FLAG_ATTR(cap_ram, CXL_DECODER_F_RAM);
-CXL_DECODER_FLAG_ATTR(cap_type2, CXL_DECODER_F_TYPE2);
-CXL_DECODER_FLAG_ATTR(cap_type3, CXL_DECODER_F_TYPE3);
+CXL_DECODER_FLAG_ATTR(cap_type2, CXL_DECODER_F_DEVMEM);
+CXL_DECODER_FLAG_ATTR(cap_type3, CXL_DECODER_F_HOSTONLY);
CXL_DECODER_FLAG_ATTR(locked, CXL_DECODER_F_LOCK);
CXL_DECODER_FLAG_ATTR(cap_bi, CXL_DECODER_F_BI);
@@ -364,8 +364,8 @@ static bool can_create_pmem(struct cxl_root_decoder *cxlrd)
unsigned long flags = cxlrd->cxlsd.cxld.flags;
unsigned long hdm_h, hdm_db;
- hdm_h = CXL_DECODER_F_TYPE3 | CXL_DECODER_F_PMEM;
- hdm_db = CXL_DECODER_F_TYPE2 | CXL_DECODER_F_BI | CXL_DECODER_F_PMEM;
+ hdm_h = CXL_DECODER_F_HOSTONLY | CXL_DECODER_F_PMEM;
+ hdm_db = CXL_DECODER_F_DEVMEM | CXL_DECODER_F_BI | CXL_DECODER_F_PMEM;
return (flags & hdm_h) == hdm_h || (flags & hdm_db) == hdm_db;
}
@@ -375,8 +375,8 @@ static bool can_create_ram(struct cxl_root_decoder *cxlrd)
unsigned long flags = cxlrd->cxlsd.cxld.flags;
unsigned long hdm_h, hdm_db;
- hdm_h = CXL_DECODER_F_TYPE3 | CXL_DECODER_F_RAM;
- hdm_db = CXL_DECODER_F_TYPE2 | CXL_DECODER_F_BI | CXL_DECODER_F_RAM;
+ hdm_h = CXL_DECODER_F_HOSTONLY | CXL_DECODER_F_RAM;
+ hdm_db = CXL_DECODER_F_DEVMEM | CXL_DECODER_F_BI | CXL_DECODER_F_RAM;
return (flags & hdm_h) == hdm_h || (flags & hdm_db) == hdm_db;
}
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 62c5bd9e295c..5f4a11538bbf 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -295,8 +295,8 @@ int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport);
*/
#define CXL_DECODER_F_RAM BIT(0)
#define CXL_DECODER_F_PMEM BIT(1)
-#define CXL_DECODER_F_TYPE2 BIT(2)
-#define CXL_DECODER_F_TYPE3 BIT(3)
+#define CXL_DECODER_F_DEVMEM BIT(2)
+#define CXL_DECODER_F_HOSTONLY BIT(3)
#define CXL_DECODER_F_LOCK BIT(4)
#define CXL_DECODER_F_ENABLE BIT(5)
#define CXL_DECODER_F_NORMALIZED_ADDRESSING BIT(6)
--
2.39.5
next prev parent reply other threads:[~2026-07-27 19:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-27 19:35 [PATCH v6 0/9] cxl: Support Back-Invalidate Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 1/9] cxl: Add BI register probing and port initialization Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 2/9] cxl/pci: Add BI topology enable/disable Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 3/9] cxl/hdm: Add BI coherency support for endpoint decoders Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 4/9] cxl: Add HDM-DB region creation Davidlohr Bueso
2026-07-27 19:35 ` Davidlohr Bueso [this message]
2026-07-27 19:35 ` [PATCH v6 6/9] cxl/region: Log the coherency model at " Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 7/9] cxl: Move BI setup to endpoint port probe Davidlohr Bueso
2026-07-27 19:36 ` [PATCH v6 8/9] cxl/pci: Split BI capability probe from setup Davidlohr Bueso
2026-07-27 19:36 ` [PATCH v6 9/9] cxl: Allow auto-committed BI hdm decoders Davidlohr Bueso
2026-07-27 20:59 ` [PATCH v6 0/9] cxl: Support Back-Invalidate Jonathan Cameron
2026-07-27 21:26 ` Davidlohr Bueso
2026-07-27 23:02 ` Dave Jiang
2026-07-28 4:32 ` Davidlohr Bueso
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