From: Davidlohr Bueso <dave@stgolabs.net>
To: dave.jiang@intel.com
Cc: jic23@kernel.org, alison.schofield@intel.com, icheng@nvidia.com,
benjamin.cheatham@amd.com, alucerop@amd.com,
dongjoo.seo1@samsung.com, dave@stgolabs.net,
linux-kernel@vger.kernel.org
Subject: [PATCH v6 6/9] cxl/region: Log the coherency model at region creation
Date: Mon, 27 Jul 2026 12:35:58 -0700 [thread overview]
Message-ID: <20260727193601.651871-7-dave@stgolabs.net> (raw)
In-Reply-To: <20260727193601.651871-1-dave@stgolabs.net>
Region assembly emits plenty of debug information - resources,
interleave geometry, target placement - but not the coherency model
the region operates in.
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
---
drivers/cxl/core/region.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 1b8284f66e61..7c11d5788d99 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -2746,6 +2746,17 @@ void kill_regions(struct cxl_root_decoder *cxlrd)
unregister_region(cxlr);
}
+static const char *cxl_region_coherency(struct cxl_region *cxlr)
+{
+ if (cxlr->type == CXL_DECODER_HOSTONLYMEM)
+ return "HDM-H";
+
+ if (cxl_root_decoder_is_bi(cxlr->cxlrd))
+ return "HDM-DB";
+
+ return "HDM-D";
+}
+
/**
* devm_cxl_add_region - Adds a region to a decoder
* @cxlrd: root decoder
@@ -2790,8 +2801,9 @@ static struct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd,
return ERR_PTR(rc);
}
- dev_dbg(port->uport_dev, "%s: created %s\n",
- dev_name(&cxlrd->cxlsd.cxld.dev), dev_name(dev));
+ dev_dbg(port->uport_dev, "%s: created %s %s\n",
+ dev_name(&cxlrd->cxlsd.cxld.dev), cxl_region_coherency(cxlr),
+ dev_name(dev));
return cxlr;
err:
put_device(dev);
--
2.39.5
next prev parent reply other threads:[~2026-07-27 19:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-27 19:35 [PATCH v6 0/9] cxl: Support Back-Invalidate Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 1/9] cxl: Add BI register probing and port initialization Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 2/9] cxl/pci: Add BI topology enable/disable Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 3/9] cxl/hdm: Add BI coherency support for endpoint decoders Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 4/9] cxl: Add HDM-DB region creation Davidlohr Bueso
2026-07-27 19:35 ` [PATCH v6 5/9] cxl/hdm: Rename decoder coherency flags Davidlohr Bueso
2026-07-27 19:35 ` Davidlohr Bueso [this message]
2026-07-27 19:35 ` [PATCH v6 7/9] cxl: Move BI setup to endpoint port probe Davidlohr Bueso
2026-07-27 19:36 ` [PATCH v6 8/9] cxl/pci: Split BI capability probe from setup Davidlohr Bueso
2026-07-27 19:36 ` [PATCH v6 9/9] cxl: Allow auto-committed BI hdm decoders Davidlohr Bueso
2026-07-27 20:59 ` [PATCH v6 0/9] cxl: Support Back-Invalidate Jonathan Cameron
2026-07-27 21:26 ` Davidlohr Bueso
2026-07-27 23:02 ` Dave Jiang
2026-07-28 4:32 ` Davidlohr Bueso
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