[PATCH] ARM: dts: vf610: describe the L2 cache geometry

[PATCH] ARM: dts: vf610: describe the L2 cache geometry

[Mehmet Fide]

From: Mehmet Fide <mehmet.fide@screeningeagle.com>

The L2 node names the controller and its level, but not its size, line
size or set count, so cacheinfo cannot describe the last level of the
hierarchy even though the cpu node already points at it.

Fill them in from the Vybrid reference manual (NXP VFXXXRM), section
3.2.3: 8 way set associative, 512 KB, 32 byte line, so 2048 sets.

Not tested on VF610 silicon, the values come from the manual. The
matching change for the L1 caches was tested on a VF500.

Signed-off-by: Mehmet Fide <mehmet.fide@screeningeagle.com>
---
 arch/arm/boot/dts/nxp/vf/vf610.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/vf/vf610.dtsi b/arch/arm/boot/dts/nxp/vf/vf610.dtsi
index 2fba923..ea59e3d 100644
--- a/arch/arm/boot/dts/nxp/vf/vf610.dtsi
+++ b/arch/arm/boot/dts/nxp/vf/vf610.dtsi
@@ -14,6 +14,9 @@
 		reg = <0x40006000 0x1000>;
 		cache-unified;
 		cache-level = <2>;
+		cache-line-size = <32>;
+		cache-sets = <2048>;
+		cache-size = <0x80000>;
 		arm,data-latency = <3 3 3>;
 		arm,tag-latency = <2 2 2>;
 	};
-- 
2.54.0

Re: [PATCH] ARM: dts: vf610: describe the L2 cache geometry

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>


On Mon, 10 Aug 2026 17:30:01 +0200, Mehmet Fide wrote:
> The L2 node names the controller and its level, but not its size, line
> size or set count, so cacheinfo cannot describe the last level of the
> hierarchy even though the cpu node already points at it.
>
> Fill them in from the Vybrid reference manual (NXP VFXXXRM), section
> 3.2.3: 8 way set associative, 512 KB, 32 byte line, so 2048 sets.
>
> [...]

Applied to imx/dt64-intend, thanks!

[1/1] ARM: dts: vf610: describe the L2 cache geometry
      commit: a9701a0f76ed7f0b75d7d00c322d13191ef32e7f

Best regards,
--
Frank Li <Frank.Li@nxp.com>