* [PATCH v4] PCI: Ensure ATS disabled via quirk before notifying IOMMU drivers
@ 2026-08-17 20:28 David Matlack
2026-08-21 2:09 ` Baolu Lu
2026-08-21 13:19 ` Deucher, Alexander
0 siblings, 2 replies; 3+ messages in thread
From: David Matlack @ 2026-08-17 20:28 UTC (permalink / raw)
To: linux-kernel, linux-pci
Cc: Alexander Lobakin, Alex Deucher, Andy Shevchenko,
Bartosz Pawlowski, Bjorn Helgaas, Christian König,
David Woodhouse, Guchun Chen, Joerg Roedel, Lu Baolu,
Raghavendra Rao Ananta, David Matlack, Pranjal Shrivastava
Ensure that PCI devices always have ATS disable via quirk before IOMMU
drivers are notified about the device. Fix this by converting the
existing quirks from final to header fixups and changing the quirk logic
to set a new no_ats bit in struct pci_dev that prevents pci_dev.ats_cap
from ever getting set.
Use header fixups instead of early fixups since not enough of struct
pci_dev is set up in during early fixups: quirk_amd_harvest_no_ats()
needs subsystem_device and subsystem_vendor to be set.
This change ensures that pci_ats_supported() always takes quirks into
account during iommu_ops.probe_device(), when IOMMU drivers are notified
about devices, and that pci_ats_supported() returns the same value when
the device is released in iommu_ops.release_device().
The Intel IOMMU driver uses pci_ats_supported() in probe/release to
determine whether to add/remove a device from a tracking rbtree. This
strict reliance on pci_ats_supported() remaining constant between probe
and release was introduced by commit 89436f4f5412 ("iommu/vt-d: Fix
WARN_ON in iommu probe path"). Because FINAL quirks evaluate too late
(in pci_bus_add_device()), pci_ats_supported() evaluated to true during
IOMMU probe but false during release. This mismatch bypassed the rbtree
removal upon device release, leading to a later use-after-free.
Note that this fix only matters for PCI devices created after IOMMU bus
notifiers are set up (e.g. hot-plugged devices and VFs).
Fixes: a18615b1cfc0 ("PCI: Disable ATS for specific Intel IPU E2000 devices")
Fixes: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken")
Fixes: 3f1271b54edc ("PCI: Mark all AMD Navi10 and Navi14 GPU ATS as broken")
Closes: https://lore.kernel.org/linux-iommu/aYUQ_HkDJU9kjsUl@google.com/
Reviewed-by: Pranjal Shrivastava <praan@google.com>
Tested-by: Pranjal Shrivastava <praan@google.com>
Signed-off-by: David Matlack <dmatlack@google.com>
---
v4:
- Rebase onto tip of Linus' tree
- Add Pranjal's Reviewed-by and Tested-by tags
v3: https://lore.kernel.org/linux-pci/20260403222750.1215002-1-dmatlack@google.com/
v2: https://lore.kernel.org/linux-pci/20260327211649.3816010-1-dmatlack@google.com/
v1: https://lore.kernel.org/linux-pci/20260223184017.688212-1-dmatlack@google.com/
Cc: Raghavendra Rao Ananta <rananta@google.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
drivers/pci/ats.c | 2 +-
drivers/pci/quirks.c | 50 ++++++++++++++++++++++----------------------
include/linux/pci.h | 1 +
3 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
index 96efa00d9743..772fb1968f3c 100644
--- a/drivers/pci/ats.c
+++ b/drivers/pci/ats.c
@@ -21,7 +21,7 @@ void pci_ats_init(struct pci_dev *dev)
{
int pos;
- if (pci_ats_disabled())
+ if (pci_ats_disabled() || dev->no_ats)
return;
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index b09f27f7846f..34f1aee744ac 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5646,7 +5646,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
static void quirk_no_ats(struct pci_dev *pdev)
{
pci_info(pdev, "disabling ATS\n");
- pdev->ats_cap = 0;
+ pdev->no_ats = 1;
}
/*
@@ -5669,25 +5669,25 @@ static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
}
/* AMD Stoney platform GPU */
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
/* AMD Iceland dGPU */
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
/* AMD Navi10 dGPU */
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
/* AMD Navi14 dGPU */
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
/* AMD Raven platform iGPU */
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
/*
* Intel IPU E2000 revisions before C0 implement incorrect endianness
@@ -5698,15 +5698,15 @@ static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)
if (pdev->revision < 0x20)
quirk_no_ats(pdev);
}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
static bool quirk_nvidia_gpu_ats_required(struct pci_dev *pdev)
{
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 64b308b6e61c..393eb77112c9 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -546,6 +546,7 @@ struct pci_dev {
};
u16 ats_cap; /* ATS Capability offset */
u8 ats_stu; /* ATS Smallest Translation Unit */
+ u8 no_ats:1; /* ATS disabled via quirk */
#endif
#ifdef CONFIG_PCI_PRI
u16 pri_cap; /* PRI Capability offset */
base-commit: 8d3ae59288f1e7d58d76558a6ee96d533bc5019f
--
2.55.0.699.gb54405d56f-goog
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4] PCI: Ensure ATS disabled via quirk before notifying IOMMU drivers
2026-08-17 20:28 [PATCH v4] PCI: Ensure ATS disabled via quirk before notifying IOMMU drivers David Matlack
@ 2026-08-21 2:09 ` Baolu Lu
2026-08-21 13:19 ` Deucher, Alexander
1 sibling, 0 replies; 3+ messages in thread
From: Baolu Lu @ 2026-08-21 2:09 UTC (permalink / raw)
To: David Matlack, linux-kernel, linux-pci
Cc: Alexander Lobakin, Alex Deucher, Andy Shevchenko,
Bartosz Pawlowski, Bjorn Helgaas, Christian König,
David Woodhouse, Guchun Chen, Joerg Roedel,
Raghavendra Rao Ananta, Pranjal Shrivastava
On 8/18/26 04:28, David Matlack wrote:
> Ensure that PCI devices always have ATS disable via quirk before IOMMU
> drivers are notified about the device. Fix this by converting the
> existing quirks from final to header fixups and changing the quirk logic
> to set a new no_ats bit in struct pci_dev that prevents pci_dev.ats_cap
> from ever getting set.
>
> Use header fixups instead of early fixups since not enough of struct
> pci_dev is set up in during early fixups: quirk_amd_harvest_no_ats()
> needs subsystem_device and subsystem_vendor to be set.
>
> This change ensures that pci_ats_supported() always takes quirks into
> account during iommu_ops.probe_device(), when IOMMU drivers are notified
> about devices, and that pci_ats_supported() returns the same value when
> the device is released in iommu_ops.release_device().
>
> The Intel IOMMU driver uses pci_ats_supported() in probe/release to
> determine whether to add/remove a device from a tracking rbtree. This
> strict reliance on pci_ats_supported() remaining constant between probe
> and release was introduced by commit 89436f4f5412 ("iommu/vt-d: Fix
> WARN_ON in iommu probe path"). Because FINAL quirks evaluate too late
> (in pci_bus_add_device()), pci_ats_supported() evaluated to true during
> IOMMU probe but false during release. This mismatch bypassed the rbtree
> removal upon device release, leading to a later use-after-free.
>
> Note that this fix only matters for PCI devices created after IOMMU bus
> notifiers are set up (e.g. hot-plugged devices and VFs).
>
> Fixes: a18615b1cfc0 ("PCI: Disable ATS for specific Intel IPU E2000 devices")
> Fixes: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken")
> Fixes: 3f1271b54edc ("PCI: Mark all AMD Navi10 and Navi14 GPU ATS as broken")
> Closes:https://lore.kernel.org/linux-iommu/aYUQ_HkDJU9kjsUl@google.com/
> Reviewed-by: Pranjal Shrivastava<praan@google.com>
> Tested-by: Pranjal Shrivastava<praan@google.com>
> Signed-off-by: David Matlack<dmatlack@google.com>
> ---
> v4:
> - Rebase onto tip of Linus' tree
> - Add Pranjal's Reviewed-by and Tested-by tags
>
> v3:https://lore.kernel.org/linux-pci/20260403222750.1215002-1-
> dmatlack@google.com/
> v2:https://lore.kernel.org/linux-pci/20260327211649.3816010-1-
> dmatlack@google.com/
> v1:https://lore.kernel.org/linux-pci/20260223184017.688212-1-
> dmatlack@google.com/
>
> Cc: Raghavendra Rao Ananta<rananta@google.com>
> Cc: David Woodhouse<dwmw2@infradead.org>
> Cc: Lu Baolu<baolu.lu@linux.intel.com>
> Cc: Andy Shevchenko<andriy.shevchenko@linux.intel.com>
>
> drivers/pci/ats.c | 2 +-
> drivers/pci/quirks.c | 50 ++++++++++++++++++++++----------------------
> include/linux/pci.h | 1 +
> 3 files changed, 27 insertions(+), 26 deletions(-)
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v4] PCI: Ensure ATS disabled via quirk before notifying IOMMU drivers
2026-08-17 20:28 [PATCH v4] PCI: Ensure ATS disabled via quirk before notifying IOMMU drivers David Matlack
2026-08-21 2:09 ` Baolu Lu
@ 2026-08-21 13:19 ` Deucher, Alexander
1 sibling, 0 replies; 3+ messages in thread
From: Deucher, Alexander @ 2026-08-21 13:19 UTC (permalink / raw)
To: David Matlack, linux-kernel, linux-pci
Cc: Alexander Lobakin, Andy Shevchenko, Bartosz Pawlowski,
Bjorn Helgaas, Koenig, Christian, David Woodhouse, Guchun Chen,
Joerg Roedel, Lu Baolu, Raghavendra Rao Ananta,
Pranjal Shrivastava
AMD General
> -----Original Message-----
> From: David Matlack <dmatlack@google.com>
> Sent: Monday, August 17, 2026 4:28 PM
> To: linux-kernel@vger.kernel.org; linux-pci@vger.kernel.org
> Cc: Alexander Lobakin <aleksander.lobakin@intel.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; Bartosz Pawlowski
> <bartosz.pawlowski@intel.com>; Bjorn Helgaas <bhelgaas@google.com>;
> Koenig, Christian <Christian.Koenig@amd.com>; David Woodhouse
> <dwmw2@infradead.org>; Guchun Chen <guchun.chen@amd.com>; Joerg
> Roedel <jroedel@suse.de>; Lu Baolu <baolu.lu@linux.intel.com>; Raghavendra
> Rao Ananta <rananta@google.com>; David Matlack <dmatlack@google.com>;
> Pranjal Shrivastava <praan@google.com>
> Subject: [PATCH v4] PCI: Ensure ATS disabled via quirk before notifying
> IOMMU drivers
>
> Ensure that PCI devices always have ATS disable via quirk before IOMMU
> drivers are notified about the device. Fix this by converting the existing quirks
> from final to header fixups and changing the quirk logic to set a new no_ats bit
> in struct pci_dev that prevents pci_dev.ats_cap from ever getting set.
>
> Use header fixups instead of early fixups since not enough of struct pci_dev is
> set up in during early fixups: quirk_amd_harvest_no_ats() needs
> subsystem_device and subsystem_vendor to be set.
>
> This change ensures that pci_ats_supported() always takes quirks into account
> during iommu_ops.probe_device(), when IOMMU drivers are notified about
> devices, and that pci_ats_supported() returns the same value when the device
> is released in iommu_ops.release_device().
>
> The Intel IOMMU driver uses pci_ats_supported() in probe/release to
> determine whether to add/remove a device from a tracking rbtree. This strict
> reliance on pci_ats_supported() remaining constant between probe and
> release was introduced by commit 89436f4f5412 ("iommu/vt-d: Fix
> WARN_ON in iommu probe path"). Because FINAL quirks evaluate too late (in
> pci_bus_add_device()), pci_ats_supported() evaluated to true during IOMMU
> probe but false during release. This mismatch bypassed the rbtree removal
> upon device release, leading to a later use-after-free.
>
> Note that this fix only matters for PCI devices created after IOMMU bus
> notifiers are set up (e.g. hot-plugged devices and VFs).
>
> Fixes: a18615b1cfc0 ("PCI: Disable ATS for specific Intel IPU E2000 devices")
> Fixes: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken")
> Fixes: 3f1271b54edc ("PCI: Mark all AMD Navi10 and Navi14 GPU ATS as
> broken")
> Closes: https://lore.kernel.org/linux-
> iommu/aYUQ_HkDJU9kjsUl@google.com/
> Reviewed-by: Pranjal Shrivastava <praan@google.com>
> Tested-by: Pranjal Shrivastava <praan@google.com>
> Signed-off-by: David Matlack <dmatlack@google.com>
> ---
> v4:
> - Rebase onto tip of Linus' tree
> - Add Pranjal's Reviewed-by and Tested-by tags
>
> v3: https://lore.kernel.org/linux-pci/20260403222750.1215002-1-
> dmatlack@google.com/
> v2: https://lore.kernel.org/linux-pci/20260327211649.3816010-1-
> dmatlack@google.com/
> v1: https://lore.kernel.org/linux-pci/20260223184017.688212-1-
> dmatlack@google.com/
>
> Cc: Raghavendra Rao Ananta <rananta@google.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> drivers/pci/ats.c | 2 +-
> drivers/pci/quirks.c | 50 ++++++++++++++++++++++----------------------
> include/linux/pci.h | 1 +
> 3 files changed, 27 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index
> 96efa00d9743..772fb1968f3c 100644
> --- a/drivers/pci/ats.c
> +++ b/drivers/pci/ats.c
> @@ -21,7 +21,7 @@ void pci_ats_init(struct pci_dev *dev) {
> int pos;
>
> - if (pci_ats_disabled())
> + if (pci_ats_disabled() || dev->no_ats)
> return;
>
> pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS); diff --git
> a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> b09f27f7846f..34f1aee744ac 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5646,7 +5646,7 @@
> DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422,
> quirk_no_ext_tags); static void quirk_no_ats(struct pci_dev *pdev) {
> pci_info(pdev, "disabling ATS\n");
> - pdev->ats_cap = 0;
> + pdev->no_ats = 1;
> }
>
> /*
> @@ -5669,25 +5669,25 @@ static void quirk_amd_harvest_no_ats(struct
> pci_dev *pdev) }
>
> /* AMD Stoney platform GPU */
> -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4,
> quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x98e4,
> +quirk_amd_harvest_no_ats);
> /* AMD Iceland dGPU */
> -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900,
> quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x6900,
> +quirk_amd_harvest_no_ats);
> /* AMD Navi10 dGPU */
> -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f,
> quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7310,
> +quirk_amd_harvest_no_ats);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI,
> +0x7312, quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7318,
> +quirk_amd_harvest_no_ats);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI,
> +0x7319, quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x731a,
> +quirk_amd_harvest_no_ats);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI,
> +0x731b, quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x731e,
> +quirk_amd_harvest_no_ats);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI,
> +0x731f, quirk_amd_harvest_no_ats);
> /* AMD Navi14 dGPU */
> -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347,
> quirk_amd_harvest_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f,
> quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7340,
> +quirk_amd_harvest_no_ats);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI,
> +0x7341, quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x7347,
> +quirk_amd_harvest_no_ats);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI,
> +0x734f, quirk_amd_harvest_no_ats);
> /* AMD Raven platform iGPU */
> -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8,
> quirk_amd_harvest_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x15d8,
> +quirk_amd_harvest_no_ats);
>
FWIW, unrelated to this patch, but all of these AMD quirks could be removed if the device driver could opt into ATS rather than having the IOMMU enable it before the driver is loaded.
Alex
> /*
> * Intel IPU E2000 revisions before C0 implement incorrect endianness @@ -
> 5698,15 +5698,15 @@ static void quirk_intel_e2000_no_ats(struct pci_dev
> *pdev)
> if (pdev->revision < 0x20)
> quirk_no_ats(pdev);
> }
> -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451,
> quirk_intel_e2000_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452,
> quirk_intel_e2000_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453,
> quirk_intel_e2000_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454,
> quirk_intel_e2000_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455,
> quirk_intel_e2000_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457,
> quirk_intel_e2000_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459,
> quirk_intel_e2000_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a,
> quirk_intel_e2000_no_ats); -
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c,
> quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1451,
> +quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1452,
> +quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1453,
> +quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1454,
> +quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1455,
> +quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1457,
> +quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1459,
> +quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x145a,
> +quirk_intel_e2000_no_ats);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x145c,
> +quirk_intel_e2000_no_ats);
>
> static bool quirk_nvidia_gpu_ats_required(struct pci_dev *pdev) { diff --git
> a/include/linux/pci.h b/include/linux/pci.h index
> 64b308b6e61c..393eb77112c9 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -546,6 +546,7 @@ struct pci_dev {
> };
> u16 ats_cap; /* ATS Capability offset */
> u8 ats_stu; /* ATS Smallest Translation Unit */
> + u8 no_ats:1; /* ATS disabled via quirk */
> #endif
> #ifdef CONFIG_PCI_PRI
> u16 pri_cap; /* PRI Capability offset */
>
> base-commit: 8d3ae59288f1e7d58d76558a6ee96d533bc5019f
> --
> 2.55.0.699.gb54405d56f-goog
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-08-21 13:19 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-08-17 20:28 [PATCH v4] PCI: Ensure ATS disabled via quirk before notifying IOMMU drivers David Matlack
2026-08-21 2:09 ` Baolu Lu
2026-08-21 13:19 ` Deucher, Alexander
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