Re: [PATCH v7 23/24] iommu/arm-smmu-v3-kvm: Enable nesting

[Jason Gunthorpe <jgg@nvidia.com>]

On Thu, Aug 27, 2026 at 10:04:50AM +0000, Mostafa Saleh wrote:

> From S1DSS (nested in HW) to bypass (S2 in HW), the kernel STE writer
> will do a hitless update by writing DWORD 0 => CFGI => DOWRD1-3 => CFGI
> The hypervisor will transition Nested to S2 only on the first CFGI which
> is safe.

It gets tricky to reason about since the guest kernel doesn't know
about the S2 items that are changing also when it builds the
sequence.

IIRC there are also some annoying corner cases about illegal or
unpredictable STE/CDs that have caused trouble before too.

> > We really don't need two versions of this stuf, just use the
> > programmer we know it is right at this point.
> 
> The problem with that it needs to pull a lot of code out of the
> SMMUv3 driver which has things as struct arm_smmu_master.

The master is only used by the sync op to generate the correct
invalidation, you can just #define it to whatever kvm's struct is.

Lu had a series that moved this code to be properly general which
would be even better, but it seems to have got forgotten

> I will need to check how that can work, but I will try to avoid
> that, specially this is not a generic STE writer it has quite
> small transitions which shouldn't change in the future.

We've already had problems here on the viommu code, I think this is
too optimistic. I don't really want to think about a second version of
this :)

Jason