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* [PATCH v2 0/5] optimize pgtable_l4|l5_enabled
@ 2026-09-07 15:14 Jisheng Zhang
  2026-09-07 15:14 ` [PATCH v2 1/5] riscv: remove RISCV_ALTERNATIVE Kconfig option Jisheng Zhang
                   ` (4 more replies)
  0 siblings, 5 replies; 17+ messages in thread
From: Jisheng Zhang @ 2026-09-07 15:14 UTC (permalink / raw)
  To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
	Andrey Ryabinin, Alexander Potapenko, Andrey Konovalov,
	Dmitry Vyukov, Vincenzo Frascino
  Cc: linux-riscv, linux-kernel, kasan-dev

In 2022, I tried to optimize pgtable_l4|l5_enabled use static branch[3]
But as is known, static branch has some drawbacks. 

This series is another round of optmizing pgtable_l4|l5_enabled, but
with another mechanism. Below the is normal cover-letter.

The pgtable_l4|[l5]_enabled check sits at hot code path, performance
is impacted a lot. Since pgtable_l4|[l5]_enabled isn't changed after
boot, we can use alternative mechanism to optimize them.

So the question is whether we can add RISCV_ISA_EXT_SV48/SV5 and use
riscv_has_extension_*() or not. Per [1] and [2], SV48 and SV57 are ISA
exensions too. From another side, riscv_has_extension_[un]likely() and
other related functions report whether the extension is supported and
enabled on the platform. So SV48 and SV57 can be supported with current
isa extension alternative mechanism.

However, to use it to optimize pgtable_l4|l5_enabled, we have support
the "early" characteristic, I.E besides risc_isa bitmap setting, we
need to support appling alternative early before MMU on.

After that, use it to optimize pgtable_l4|l5_enabled.

For the typical access_ok(addr, 1);
before the patch:

...
auipc	a5,0xb43
lbu	a5,100(a5) # ffffffff80b51f68 <pgtable_l5_enabled>
bnez	a5,ffffffff8000ef46 <foo+0x56>
auipc	a5,0xb43
lbu	a5,91(a5) # ffffffff80b51f69 <pgtable_l4_enabled>
beqz	a5,ffffffff8000ef5a <foo+0x6a>
...

after the patch:
These memory load and test branch instructions are replaced with only
two j or nop instructions.

Initial test lmbench's lat_syscall write on TH1520 platforms shows that
the write syscall latency is reduced by about 2.38%.

After that, introduce RISCV_ISA_SV48 and RISCV_ISA_SV57 under NONPORTABLE,
so that the embedded platforms can choose the best option themselves,
while still keep the feature of unified one kernel Image for all SV39, SV48
and SV57 when !NONPORTABLE.

Tested on TH1520 platforms with both RISCV_ISA_SV48 and RISCV_ISA_SV48
disabled, we saved 20 instructions for access_ok(addr, 1)

Link: https://github.com/riscv/riscv-isa-manual/blob/main/src/profiles/profiles.adoc [1]
Link: https://riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+ISA+Extensions [2]
Link: https://lore.kernel.org/linux-riscv/20220821140918.3613-1-jszhang@kernel.org/ [3]

Since v1:
  - use current isa extension to support SV48/SV57
  - collect Reviewed-by tag
  - add patch4 to introduce RISCV_ISA_SV48 and RISCV_ISA_SV57 under
    NONPORTABLE
  - add patch5 to unexport _pgtable_l4_enabled and _pgtable_l5_enabled



Jisheng Zhang (5):
  riscv: remove RISCV_ALTERNATIVE Kconfig option
  riscv: convert pgtable_l4|l5_enabled to inline function
  riscv: support early isa ext and use it to optimize
    pgtable_l4|l5_enabled
  riscv: RISCV_ISA_SV48 and RISCV_ISA_SV57 under NONPORTABLE
  riscv: mm: unexport _pgtable_l4_enabled and _pgtable_l5_enabled

 arch/riscv/Kconfig                          | 48 ++++++------
 arch/riscv/Kconfig.errata                   |  5 +-
 arch/riscv/include/asm/alternative-macros.h | 24 ------
 arch/riscv/include/asm/alternative.h        | 12 +--
 arch/riscv/include/asm/cpufeature-macros.h  | 10 +--
 arch/riscv/include/asm/cpufeature.h         |  8 +-
 arch/riscv/include/asm/hwcap.h              |  2 +
 arch/riscv/include/asm/pgalloc.h            | 14 ++--
 arch/riscv/include/asm/pgtable-32.h         |  4 +-
 arch/riscv/include/asm/pgtable-64.h         | 74 ++++++++++++++-----
 arch/riscv/include/asm/pgtable.h            |  4 +-
 arch/riscv/include/asm/vendor_extensions.h  | 18 ++---
 arch/riscv/include/asm/vmalloc.h            |  5 +-
 arch/riscv/kernel/Makefile                  |  2 +-
 arch/riscv/kernel/alternative.c             | 24 ++++--
 arch/riscv/kernel/cpu.c                     |  4 +-
 arch/riscv/kernel/cpufeature.c              | 62 ++++++++++++----
 arch/riscv/mm/init.c                        | 81 +++++++++++++--------
 arch/riscv/mm/kasan_init.c                  | 20 ++---
 arch/riscv/mm/pgtable.c                     |  4 +-
 arch/riscv/mm/ptdump.c                      |  4 +-
 21 files changed, 238 insertions(+), 191 deletions(-)

-- 
2.53.0


^ permalink raw reply	[flat|nested] 17+ messages in thread
end of thread, other threads:[~2026-09-09 15:21 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-09-07 15:14 [PATCH v2 0/5] optimize pgtable_l4|l5_enabled Jisheng Zhang
2026-09-07 15:14 ` [PATCH v2 1/5] riscv: remove RISCV_ALTERNATIVE Kconfig option Jisheng Zhang
2026-09-07 15:14 ` [PATCH v2 2/5] riscv: convert pgtable_l4|l5_enabled to inline function Jisheng Zhang
2026-09-07 15:14 ` [PATCH v2 3/5] riscv: support early isa ext and use it to optimize pgtable_l4|l5_enabled Jisheng Zhang
2026-09-07 16:39   ` Conor Dooley
2026-09-08  3:43     ` Jisheng Zhang
2026-09-08 13:00       ` Conor Dooley
2026-09-08 23:46         ` Jisheng Zhang
2026-09-09 11:49           ` Conor Dooley
2026-09-09 15:01             ` Jisheng Zhang
2026-09-07 15:14 ` [PATCH v2 4/5] riscv: RISCV_ISA_SV48 and RISCV_ISA_SV57 under NONPORTABLE Jisheng Zhang
2026-09-07 16:21   ` Conor Dooley
2026-09-08  3:49     ` Jisheng Zhang
2026-09-08 13:07       ` Conor Dooley
2026-09-08 23:48         ` Jisheng Zhang
2026-09-09 11:08           ` Conor Dooley
2026-09-07 15:14 ` [PATCH v2 5/5] riscv: mm: unexport _pgtable_l4_enabled and _pgtable_l5_enabled Jisheng Zhang

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