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From: Herve Codina <herve.codina@bootlin.com>
To: Wolfram Sang <wsa+renesas@sang-engineering.com>,
	Herve Codina <herve.codina@bootlin.com>,
	Daniel Lezcano <daniel.lezcano@kernel.org>,
	Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>
Cc: linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org,
	Pascal Eberhard <pascal.eberhard@se.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH v4 2/4] clocksource/drivers: Add support for the Renesas RZ/N1 timers
Date: Wed, 9 Sep 2026 11:44:49 +0200	[thread overview]
Message-ID: <20260909114449.1d1ff12d@bootlin.com> (raw)
In-Reply-To: <20260721082952.215691-3-herve.codina@bootlin.com>

Hi Thomas, Daniel,

On Tue, 21 Jul 2026 10:29:48 +0200
"Herve Codina (Schneider Electric)" <herve.codina@bootlin.com> wrote:

> The Renesas RZ/N1 timer block controller is the controller in charge of
> timers available in the Renesas RZ/N1 SoCs family.
> 
> This controller handles 8 timers:
>   - 6 16-bit timers
>   - 2 32-bit timers
> 
> Each timer has its own interrupt, its own prescaler that can be used to
> divide the clock by 25 and all of them can work in either one-shot or
> periodic mode.
> 
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
> ---
>  drivers/clocksource/Kconfig      |  11 +
>  drivers/clocksource/Makefile     |   1 +
>  drivers/clocksource/timer-rzn1.c | 487 +++++++++++++++++++++++++++++++
>  3 files changed, 499 insertions(+)
>  create mode 100644 drivers/clocksource/timer-rzn1.c
> 

Sashiko as reported issues [0] and among them, I really don't know what to do.
--- 8< ---
  [Severity: High]
  Will using a 16-bit timer for the system clocksource break NO_HZ_IDLE?

  Since the 16-bit timer is fed by a 1 MHz clock (clock_rate / 25), it will
  wrap every ~65.5 milliseconds. Will this short wrap period force the core
  timekeeping code to wake the system extremely frequently just to accumulate
  time?

  Would it be better to dedicate one of the available 32-bit timers to act
  as the system clocksource and sched_clock?
--- 8< ---

Those 32-bit timers are assigned by the driver code to per-cpu clockevent
timers.

I could use one of the 32-bit timers for clocksource and sched_clock but this
also means the per-cpu clockevent timers will be 16-bit instead of 32-bit
timers.

Maintainers, what is better to do ?
  a) 16-bit clocksource and sched_clock + 32-bit per-cpu clockevent timers
or
  b) 32-bit clocksource and sched_clock + 16-bit per-cpu clockevent timers

[0] https://lore.kernel.org/all/20260721084351.CDA391F00A3A@smtp.kernel.org/

Best regards,
Hervé


  parent reply	other threads:[~2026-09-09  9:44 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-21  8:29 [PATCH v4 0/4] timers: Add support for RZ/N1 SoCs timers Herve Codina (Schneider Electric)
2026-07-21  8:29 ` [PATCH v4 1/4] dt-bindings: timer: Add the Renesas RZ/N1 timer Herve Codina (Schneider Electric)
2026-08-04 20:06   ` Wolfram Sang
2026-08-05  7:46     ` Geert Uytterhoeven
2026-09-09 10:06       ` Herve Codina
2026-07-21  8:29 ` [PATCH v4 2/4] clocksource/drivers: Add support for the Renesas RZ/N1 timers Herve Codina (Schneider Electric)
2026-08-04 20:30   ` Wolfram Sang
2026-08-05  7:31   ` Wolfram Sang
2026-09-09  9:44   ` Herve Codina [this message]
2026-07-21  8:29 ` [PATCH v4 3/4] ARM: dts: r9a06g032: Add support for timers Herve Codina (Schneider Electric)
2026-08-04 20:30   ` Wolfram Sang
2026-07-21  8:29 ` [PATCH v4 4/4] MAINTAINERS: Add the Renesas RZ/N1 timers driver entry Herve Codina (Schneider Electric)
2026-08-04 20:12   ` Wolfram Sang

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