[PATCH] dmaengine: mv_xor: add missing dma_wmb() barriers before descriptor chain start

[PATCH] dmaengine: mv_xor: add missing dma_wmb() barriers before descriptor chain start

[Rosen Penev]

The descriptor data written to coherent memory must be visible to the
DMA engine before the HW registers that trigger processing are written.

Add a dma_wmb() before mv_chan_set_next_descriptor() in
mv_chan_start_new_chain() to order descriptor fields before the
descriptor-pointer write.

Add a dma_wmb() after mv_desc_set_next_desc() in
mv_chan_handle_chain_append() to order the chain link write before
the subsequent check of the current-descriptor register. Without the
barrier the hardware may observe stale descriptor data.

Fixes: ff7b04796d98 ("DMA engine driver for Marvell XOR engine")
Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
 drivers/dma/mv_xor.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 24f22db5dfa1..6db7dafac9c8 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -181,6 +181,7 @@ static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan,
 	dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
 		__func__, __LINE__, sw_desc);
 
+	dma_wmb();
 	/* set the hardware chain */
 	mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
 
@@ -409,6 +410,7 @@ mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
 
 		/* fix up the hardware chain */
 		mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys);
+		dma_wmb();
 
 		/* if the channel is not busy */
 		if (!mv_chan_is_busy(mv_chan)) {
-- 
2.55.0

Re: [PATCH] dmaengine: mv_xor: add missing dma_wmb() barriers before descriptor chain start

[Frank Li]

On Wed, Sep 09, 2026 at 04:46:46PM -0700, Rosen Penev wrote:
> The descriptor data written to coherent memory must be visible to the
> DMA engine before the HW registers that trigger processing are written.
>
> Add a dma_wmb() before mv_chan_set_next_descriptor() in
> mv_chan_start_new_chain() to order descriptor fields before the
> descriptor-pointer write.
>
> Add a dma_wmb() after mv_desc_set_next_desc() in
> mv_chan_handle_chain_append() to order the chain link write before
> the subsequent check of the current-descriptor register. Without the
> barrier the hardware may observe stale descriptor data.
>
> Fixes: ff7b04796d98 ("DMA engine driver for Marvell XOR engine")
> Assisted-by: opencode:big-pickle
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
>  drivers/dma/mv_xor.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
> index 24f22db5dfa1..6db7dafac9c8 100644
> --- a/drivers/dma/mv_xor.c
> +++ b/drivers/dma/mv_xor.c
> @@ -181,6 +181,7 @@ static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan,
>  	dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
>  		__func__, __LINE__, sw_desc);
>
> +	dma_wmb();
>  	/* set the hardware chain */
>  	mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
>
> @@ -409,6 +410,7 @@ mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
>
>  		/* fix up the hardware chain */
>  		mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys);
> +		dma_wmb();

mv_chan_set_next_descriptor() implement is wrong, it should use writel()
instead of writel_relax().

Frank

>
>  		/* if the channel is not busy */
>  		if (!mv_chan_is_busy(mv_chan)) {
> --
> 2.55.0
>