* [RFC PATCH net-next] net: pcs: airoha: add support for Airoha AN7583 SoC
@ 2026-09-11 7:23 Christian Marangi
0 siblings, 0 replies; only message in thread
From: Christian Marangi @ 2026-09-11 7:23 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Christian Marangi,
linux-kernel, netdev
Add support for Airoha AN7583 PCS. This use a new analog PHY
implementation that doesn't require manual calibration but makes use of
internal algo to lock to the center of the band EYE.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
This depends on series [1] and posed as reference for AN7583 integration.
[1] https://lore.kernel.org/all/20260901083001.8044-1-ansuelsmth@gmail.com/
drivers/net/pcs/airoha/Kconfig | 7 +
drivers/net/pcs/airoha/Makefile | 3 +
drivers/net/pcs/airoha/pcs-airoha-common.c | 173 +-
drivers/net/pcs/airoha/pcs-airoha.h | 450 ++++
drivers/net/pcs/airoha/pcs-an7583.c | 2349 ++++++++++++++++++++
5 files changed, 2972 insertions(+), 10 deletions(-)
create mode 100644 drivers/net/pcs/airoha/pcs-an7583.c
diff --git a/drivers/net/pcs/airoha/Kconfig b/drivers/net/pcs/airoha/Kconfig
index 1aa4c0d33b87..8153276b3424 100644
--- a/drivers/net/pcs/airoha/Kconfig
+++ b/drivers/net/pcs/airoha/Kconfig
@@ -11,3 +11,10 @@ config PCS_AIROHA_AN7581
help
This module provides helper to phylink for managing the Airoha
AN7581 PCS for SoC Ethernet and PON SERDES.
+
+config PCS_AIROHA_AN7583
+ tristate "Airoha AN7583 PCS driver"
+ select PCS_AIROHA
+ help
+ This module provides helper to phylink for managing the Airoha
+ AN7583 PCS for SoC Ethernet and PON SERDES.
diff --git a/drivers/net/pcs/airoha/Makefile b/drivers/net/pcs/airoha/Makefile
index c5201d5cc356..3fd5e446744f 100644
--- a/drivers/net/pcs/airoha/Makefile
+++ b/drivers/net/pcs/airoha/Makefile
@@ -5,3 +5,6 @@ pcs-airoha-objs := pcs-airoha-common.o
ifdef CONFIG_PCS_AIROHA_AN7581
pcs-airoha-objs += pcs-an7581.o
endif
+ifdef CONFIG_PCS_AIROHA_AN7583
+pcs-airoha-objs += pcs-an7583.o
+endif
diff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c
index d9ec0e97b746..18200d796d81 100644
--- a/drivers/net/pcs/airoha/pcs-airoha-common.c
+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c
@@ -21,6 +21,7 @@
static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
phy_interface_t interface)
{
+ struct device *dev = priv->dev;
u32 xsi_sel;
switch (interface) {
@@ -38,6 +39,12 @@ static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
AIROHA_SCU_ETH_XSI_SEL,
xsi_sel);
+
+ /* AN7583 require additional setting */
+ if (device_is_compatible(dev, "airoha,an7583-pcs-eth"))
+ regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+ AIROHA_SCU_ETH_MAC_SEL,
+ AIROHA_SCU_ETH_MAC_SEL_XFI);
}
static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
@@ -71,7 +78,7 @@ static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
wan_sel);
}
-static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,
+static void an7581_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,
int index, phy_interface_t interface)
{
u32 xsi_sel;
@@ -111,6 +118,26 @@ static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,
}
}
+static void an7583_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ if (priv->phy)
+ return;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI1_SEL,
+ xsi_sel);
+}
+
static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
int index, phy_interface_t interface)
{
@@ -125,7 +152,10 @@ static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
airoha_pcs_setup_scu_pon(priv, interface);
break;
case AIROHA_PCS_PCIE:
- airoha_pcs_setup_scu_pcie(priv, index, interface);
+ if (device_is_compatible(priv->dev, "airoha,an7581-pcs-pcie"))
+ an7581_pcs_setup_scu_pcie(priv, index, interface);
+ else
+ an7583_pcs_setup_scu_pcie(priv, index, interface);
break;
case AIROHA_PCS_USB:
break;
@@ -146,18 +176,25 @@ static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv, int index)
{
+ const struct airoha_pcs_match_data *data = priv->data;
struct airoha_pcs_maps *maps = &priv->maps[index];
regmap_set_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
AIROHA_PCS_HSGMII_XFI_SEL);
/* Disable Hibernation */
- regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
- AIROHA_PCS_USXGMII_SPEED_SEL_H);
+ if (data->hibernation_workaround)
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+ AIROHA_PCS_USXGMII_SPEED_SEL_H);
/* FIXME: wait Airoha */
/* Avoid PCS sending garbage to MAC in some HW revision (E0) */
- regmap_write(maps->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+ if (data->usxgmii_ber_time_fixup)
+ regmap_write(maps->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+
+ if (data->usxgmii_rx_gb_out_vld_tweak)
+ regmap_clear_bits(maps->usxgmii_pcs, AN7583_PCS_USXGMII_RTL_MODIFIED,
+ AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD);
}
static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv, int index)
@@ -513,6 +550,13 @@ static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
}
+
+ if (data->usxgmii_xfi_mode_sel &&
+ neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_XFI_MODE_TX_SEL |
+ AIROHA_PCS_USXGMII_XFI_MODE_RX_SEL);
}
/* Clear any force bit that my be set by bootloader */
@@ -1017,10 +1061,14 @@ static int airoha_pcs_usb_alloc_maps(struct platform_device *pdev,
if (ret)
return ret;
+ /* For AN7583 PCS ANA is controlled by PHY driver */
+ if (device_is_compatible(&pdev->dev, "airoha,an7583-pcs-usb"))
+ return 0;
+
return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
}
-static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev,
+static int an7581_pcs_pcie_alloc_maps(struct platform_device *pdev,
struct airoha_pcs_priv *priv)
{
struct airoha_pcs_maps *maps = priv->maps;
@@ -1085,6 +1133,60 @@ static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev,
return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
}
+static int an7583_pcs_pcie_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = priv->maps;
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps[0].pcs_mac);
+ if (ret)
+ return ret;
+
+ /* On AN7583 PCS MAC is shared by SGMII/HSGMII is provided by PCIe1 PHY
+ * and USXGMII is provided by PCIE0 ANA and PMA.
+ */
+ if (priv->phy) {
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an0", &maps[0].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs0", &maps[0].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp0", &maps[0].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii0", &maps[0].multi_sgmii);
+ if (ret)
+ return ret;
+ } else {
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp1", &maps[0].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii1", &maps[0].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii1", &maps[0].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static struct phylink_pcs *airoha_pcs_xlate(struct fwnode_reference_args *pcsspec,
void *data)
{
@@ -1144,14 +1246,19 @@ static int airoha_pcs_probe(struct platform_device *pdev)
priv->dev = dev;
priv->data = data;
- if (data->port_type == AIROHA_PCS_USB) {
+ if (data->port_type == AIROHA_PCS_USB ||
+ device_is_compatible(dev, "airoha,an7583-pcs-pcie")) {
struct phy *phy;
+ /* For AN7583 PCIe PCS PHY is optional */
phy = devm_phy_get(dev, NULL);
- if (IS_ERR(phy))
+ if (IS_ERR(phy) &&
+ (data->port_type == AIROHA_PCS_USB ||
+ PTR_ERR(phy) != -ENODEV))
return dev_err_probe(dev, PTR_ERR(phy), "failed to get phy\n");
- priv->phy = phy;
+ if (!IS_ERR(phy))
+ priv->phy = phy;
}
switch (data->port_type) {
@@ -1163,7 +1270,10 @@ static int airoha_pcs_probe(struct platform_device *pdev)
break;
case AIROHA_PCS_PCIE:
- ret = airoha_pcs_pcie_alloc_maps(pdev, priv);
+ if (device_is_compatible(dev, "airoha,an7581-pcs-pcie"))
+ ret = an7581_pcs_pcie_alloc_maps(pdev, priv);
+ else
+ ret = an7583_pcs_pcie_alloc_maps(pdev, priv);
if (ret)
return ret;
@@ -1252,6 +1362,8 @@ static int airoha_pcs_probe(struct platform_device *pdev)
static const struct airoha_pcs_match_data an7581_pcs_eth = {
.num_port = 1,
.port_type = AIROHA_PCS_ETH,
+ .hibernation_workaround = true,
+ .usxgmii_ber_time_fixup = true,
.alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
.bringup = an7581_pcs_bringup,
.link_up = an7581_pcs_phya_link_up,
@@ -1261,6 +1373,8 @@ static const struct airoha_pcs_match_data an7581_pcs_eth = {
static const struct airoha_pcs_match_data an7581_pcs_pon = {
.num_port = 1,
.port_type = AIROHA_PCS_PON,
+ .hibernation_workaround = true,
+ .usxgmii_ber_time_fixup = true,
.alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
.bringup = an7581_pcs_bringup,
.link_up = an7581_pcs_phya_link_up,
@@ -1269,6 +1383,8 @@ static const struct airoha_pcs_match_data an7581_pcs_pon = {
static const struct airoha_pcs_match_data an7581_pcs_pcie = {
.num_port = 2,
.port_type = AIROHA_PCS_PCIE,
+ .hibernation_workaround = true,
+ .usxgmii_ber_time_fixup = true,
.alloc_regmap_fields = an7581_pcs_pcie_alloc_regmap_fields,
.bringup = an7581_pcs_bringup,
.link_up = an7581_pcs_phya_link_up,
@@ -1280,11 +1396,48 @@ static const struct airoha_pcs_match_data an7581_pcs_usb = {
.bringup = an7581_pcs_usb_bringup,
};
+static const struct airoha_pcs_match_data an7583_pcs_eth = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_ETH,
+ .usxgmii_rx_gb_out_vld_tweak = true,
+ .usxgmii_xfi_mode_sel = true,
+ .bringup = an7583_pcs_common_phya_bringup,
+ .link_up = an7583_pcs_common_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7583_pcs_pon = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_PON,
+ .usxgmii_rx_gb_out_vld_tweak = true,
+ .usxgmii_xfi_mode_sel = true,
+ .bringup = an7583_pcs_common_phya_bringup,
+ .link_up = an7583_pcs_common_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7583_pcs_pcie = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_PCIE,
+ .usxgmii_rx_gb_out_vld_tweak = true,
+ .usxgmii_xfi_mode_sel = true,
+ .bringup = an7583_pcs_common_phya_bringup,
+ .link_up = an7583_pcs_common_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7583_pcs_usb = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_USB,
+ .bringup = an7583_pcs_usb_phya_bringup,
+};
+
static const struct of_device_id airoha_pcs_of_table[] = {
{ .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
{ .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
{ .compatible = "airoha,an7581-pcs-pcie", .data = &an7581_pcs_pcie },
{ .compatible = "airoha,an7581-pcs-usb", .data = &an7581_pcs_usb },
+ { .compatible = "airoha,an7583-pcs-eth", .data = &an7583_pcs_eth },
+ { .compatible = "airoha,an7583-pcs-pon", .data = &an7583_pcs_pon },
+ { .compatible = "airoha,an7583-pcs-pcie", .data = &an7583_pcs_pcie },
+ { .compatible = "airoha,an7583-pcs-usb", .data = &an7583_pcs_usb },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
diff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h
index 8a76d51b5d2c..d36b5f2fc48c 100644
--- a/drivers/net/pcs/airoha/pcs-airoha.h
+++ b/drivers/net/pcs/airoha/pcs-airoha.h
@@ -14,6 +14,9 @@
#define AIROHA_SCU_PDIDR 0x5c
#define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0)
#define AIROHA_SCU_WAN_CONF 0x70
+#define AIROHA_SCU_ETH_MAC_SEL BIT(24)
+#define AIROHA_SCU_ETH_MAC_SEL_XFI FIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x0)
+#define AIROHA_SCU_ETH_MAC_SEL_PON FIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x1)
#define AIROHA_SCU_WAN_SEL GENMASK(7, 0)
#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
@@ -87,8 +90,14 @@
/* HSGMII_PCS */
#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0
#define AIROHA_PCS_TBI_10B_MODE BIT(30)
+#define AIROHA_PCS_SGMIII_ENA BIT(27)
+#define AIROHA_PCS_SD_SIG_DET BIT(26)
#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24)
+#define AIROHA_PCS_SGMII_1US_TIMER GENMASK(23, 16)
+#define AIROHA_PCS_RX_CLK_ENA BIT(15)
+#define AIROHA_PCS_GMII_TXCLK_ENA BIT(14)
#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12)
+#define AIROHA_PCS_AN_ENABLE BIT(10)
#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8
#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0)
#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14
@@ -192,6 +201,9 @@
#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2)
#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1)
#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_LIK_STS_1 0x518
+#define AIROHA_PCS_PAUSE_STS_P2 BIT(6)
+#define AIROHA_PCS_PAUSE_STS_P1 BIT(5)
/* HSGMII_RATE_ADP */
#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0
@@ -287,6 +299,8 @@
#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c
#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320
+#define AIROHA_PCS_USXGMII_XFI_MODE_TX_SEL BIT(20)
+#define AIROHA_PCS_USXGMII_XFI_MODE_RX_SEL BIT(16)
#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12)
#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8)
#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)
@@ -294,9 +308,27 @@
#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)
#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)
#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)
+#define AN7583_PCS_USXGMII_RTL_MODIFIED 0x334
+#define AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD BIT(25)
/* PMA_PHYA */
#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0
+#define AIROHA_PCS_ANA_CMN_VREFSEL GENMASK(18, 16)
+#define AIROHA_PCS_ANA_CMN_VREFSEL_8V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x0)
+#define AIROHA_PCS_ANA_CMN_VREFSEL_8_25V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x1)
+#define AIROHA_PCS_ANA_CMN_VREFSEL_8_5V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x2)
+#define AIROHA_PCS_ANA_CMN_VREFSEL_8_75V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x3)
+#define AIROHA_PCS_ANA_CMN_VREFSEL_9V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x4)
+#define AIROHA_PCS_ANA_CMN_VREFSEL_9_25V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x5)
+#define AIROHA_PCS_ANA_CMN_VREFSEL_9_5V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x6)
+#define AIROHA_PCS_ANA_CMN_VREFSEL_9_75V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x7)
+#define AIROHA_PCS_ANA_CMN_VREFSEL GENMASK(18, 16)
+/* GENMASK(2, 0) input selection from 0 to 7
+ * BIT(3) OPAMP and path EN
+ * BIT(4) Current path measurement
+ * BIT(5) voltage/current path to PAD
+ */
+#define AIROHA_PCS_ANA_CMN_MPXSELTOP_DC GENMASK(13, 8)
#define AIROHA_PCS_ANA_CMN_EN BIT(0)
#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4
#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24)
@@ -389,6 +421,8 @@
#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16)
#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8)
#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO BIT(5)
+#define AIROHA_PCS_ANA_PXP_JCPLL_FREQ_MEAS_EN 0x4c
+#define AIROHA_PCS_ANA_TXPLL_IB_EXT_EN BIT(24)
#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50
#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24)
#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16)
@@ -412,6 +446,9 @@
#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 0x3
#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8)
#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_PHY_CK1_EN 0x60
+#define AIROHA_PCS_ANA_TXPLL_PHY_CK2_EN BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_PHY_CK1_EN BIT(0)
#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64
#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24)
#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16)
@@ -477,16 +514,41 @@
#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16)
#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VTP_EN 0x88
+#define AIROHA_PCS_ANA_TXPLL_VTP GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_VTP_EN BIT(0)
#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94
+#define AIROHA_PCS_ANA_TXPLL_POSTDIV_D256_EN BIT(25) /* 0: 128 1: 256 */
+#define AIROHA_PCS_ANA_TXPLL_VCO_KBAND_MEAS_EN BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_FREQ_MEAS_EN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_VREF_SEL BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_VREF_SEL_VBG FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x0)
+#define AIROHA_PCS_ANA_TXPLL_VREF_SEL_AVDD FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x1)
#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AN7583_PCS_ANA_PXP_TXPLL_CHP_DOUBLE_EN 0x98
+#define AIROHA_PCS_ANA_TXPLL_SPARE_L BIT(0) /* ICHP_DOUBLE */
+#define AIROHA_PCS_ANA_PXP_PLL_MONCLK_SEL 0xa0
+#define AIROHA_PCS_ANA_TDC_AUTOEN BIT(24)
+#define AIROHA_PCS_ANA_PXP_TDC_SYNC_CK_SEL 0xa8
+#define AIROHA_PCS_ANA_PLL_LDO_CKDRV_VSEL GENMASK(17, 16)
+#define AIROHA_PCS_ANA_PLL_LDO_CKDRV_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_TX_TXLBRC_EN 0xc0
+#define AIROHA_PCS_ANA_TX_TERMCAL_VREF_L GENMASK(26, 24)
+#define AIROHA_PCS_ANA_TX_TERMCAL_VREF_H GENMASK(18, 16)
#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4
#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24)
#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TX_TERMCAL_SELPN 0xc8
+#define AIROHA_PCS_ANA_TX_TDC_CK_SEL GENMASK(17, 16)
#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc
#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24)
#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16)
#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR 0x0
#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_FORCE BIT(8)
+#define AIROHA_PCS_ANA_RX_BUSBIT_SEL BIT(0)
+#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_8BIT FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x0)
+#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_16BIT FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x1)
#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4
#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16)
#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
@@ -494,6 +556,16 @@
#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18)
#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_RX_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_REV_0_PLEYE_XOR_MON_EN BIT(0)
#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8
#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24)
#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16)
@@ -502,6 +574,8 @@
#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8)
#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_BOT_LIM 0xe0
+#define AIROHA_PCS_ANA_CDR_LPF_BOT_LIM GENMASK(18, 0)
#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8
#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8)
#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0)
@@ -517,6 +591,19 @@
#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16)
#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8)
#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_CKREF_DIV 0x100
+#define AIROHA_PCS_ANA_CDR_PR_RSTB_BYPASS BIT(16)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x0)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x1)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x2)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_X FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x3)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_TDC_REF_SEL 0x108
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1 GENMASK(25, 24)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x0)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x1)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x2)
+#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_X FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x3)
#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c
#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24)
#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19)
@@ -526,6 +613,7 @@
#define AIROHA_PCS_ANA_CDR_PR_MONPR_EN BIT(0)
#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110
#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_RX_DAC_RANGE_EYE GENMASK(9, 8)
#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114
#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24)
#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16)
@@ -964,7 +1052,70 @@
#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0
#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24)
#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4
+#define AIROHA_PCS_PMA_LCPLL_CK_STB_TIMER GENMASK(31, 24)
+#define AIROHA_PCS_PMA_LCPLL_PCW_MAN_LOAD_TIMER GENMASK(23, 16)
+#define AIROHA_PCS_PMA_LCPLL_EN_TIMER GENMASK(15, 8)
#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0)
+#define AIROHA_PCS_PMA_LCPLL_TDC_PW_0 0x10
+#define AIROHA_PCS_PMA_LCPLL_TDC_DIG_PWDB BIT(0)
+#define AIROHA_PCS_PMA_LCPLL_TDC_PW_5 0x24
+#define AIROHA_PCS_PMA_LCPLL_TDC_SYNC_IN_MODE BIT(24)
+#define AIROHA_PCS_PMA_LCPLL_AUTOK_TDC BIT(16)
+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_0 0x28
+#define AIROHA_PCS_PMA_LCPLL_KI GENMASK(10, 8)
+#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC GENMASK(1, 0)
+#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x0)
+#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x1)
+#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x2)
+#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x3)
+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_1 0x2c
+#define AIROHA_PCS_PMA_LCPLL_A_TDC GENMASK(11, 8)
+#define AIROHA_PCS_PMA_LCPLL_GPON_SEL BIT(0)
+#define AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_EPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x0)
+#define AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_GPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x1)
+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_3 0x34
+#define AIROHA_PCS_PMA_LCPLL_NCPO_LOAD BIT(8)
+#define AIROHA_PCS_PMA_LCPLL_NCPO_SHIFT GENMASK(1, 0)
+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_5 0x3c
+#define AIROHA_PCS_PMA_LCPLL_TDC_AUTOPW_NCPO BIT(16)
+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_6 0x40
+#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY GENMASK(9, 8)
+#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x0)
+#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D1 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x1)
+#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D2 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x2)
+#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D3 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x3)
+#define AIROHA_PCS_PMA_LCPLL_TDC_PCW_1 0x48
+#define AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)
+#define AIROHA_PCS_PMA_LCPLL_TDC_PCW_2 0x4c
+#define AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_EPON GENMASK(30, 0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_0 0x68
+#define AIROHA_PCS_PMA_X_MAX GENMASK(26, 16)
+#define AIROHA_PCS_PMA_X_MIN GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_1 0x6c
+#define AIROHA_PCS_PMA_INDEX_MODE BIT(16)
+#define AIROHA_PCS_PMA_Y_MAX GENMASK(14, 8)
+#define AIROHA_PCS_PMA_Y_MIN GENMASK(6, 0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_2 0x70
+#define AIROHA_PCS_PMA_EYEDUR GENMASK(19, 0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_3 0x74
+#define AIROHA_PCS_PMA_EYE_NEXTPTS BIT(16)
+#define AIROHA_PCS_PMA_EYE_NEXTPTS_TOGGLE BIT(8)
+#define AIROHA_PCS_PMA_EYE_NEXTPTS_SEL BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_0 0x78
+#define AIROHA_PCS_PMA_EYECNT_VTH GENMASK(15, 8)
+#define AIROHA_PCS_PMA_EYECNT_HTH GENMASK(7, 0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_1 0x7c
+#define AIROHA_PCS_PMA_EO_VTH GENMASK(23, 16)
+#define AIROHA_PCS_PMA_EO_HTH GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0 0x80
+#define AIROHA_PCS_PMA_EYE_MASK GENMASK(31, 24)
+#define AIROHA_PCS_PMA_CNTFOREVER BIT(16)
+#define AIROHA_PCS_PMA_CNTLEN GENMASK(9, 0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1 0x84
+#define AIROHA_PCS_PMA_FORCE_EYEDUR_INIT_B BIT(24)
+#define AIROHA_PCS_PMA_FORCE_EYEDUR_EN BIT(16)
+#define AIROHA_PCS_PMA_DISB_EYEDUR_INIT_B BIT(8)
+#define AIROHA_PCS_PMA_DISB_EYEDUR_EN BIT(0)
#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88
#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8)
#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0)
@@ -996,14 +1147,49 @@
#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0)
#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104
#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0 0x108
+#define AIROHA_PCS_PMA_DISB_RX_FEOS_EN BIT(24)
+#define AIROHA_PCS_PMA_DISB_RX_PDOS_EN BIT(16)
+#define AIROHA_PCS_PMA_DISB_RX_PICAL_EN BIT(8)
+#define AIROHA_PCS_PMA_DISB_RX_OS_EN BIT(0)
#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_DISB_RX_BLWC_EN BIT(16)
+#define AIROHA_PCS_PMA_DISB_RX_OS_RDY BIT(8)
+#define AIROHA_PCS_PMA_DISB_RX_SDCAL_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0 0x110
+#define AIROHA_PCS_PMA_FORCE_RX_FEOS_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_RX_PDOS_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_RX_PICAL_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_RX_OS_EN BIT(0)
#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_FORCE_RX_BLWC_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_RX_OS_RDY BIT(8)
+#define AIROHA_PCS_PMA_FORCE_RX_SDCAL_EN BIT(0)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_0 0x118
+#define AIROHA_PCS_PMA_VEO_MASK GENMASK(31, 24)
+#define AIROHA_PCS_PMA_HEO_MASK GENMASK(18, 8)
+#define AIROHA_PCS_PMA_EQ_EN_DELAY GENMASK(7, 0)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_1 0x11c
+#define AIROHA_PCS_PMA_B_ZERO_SEL BIT(24)
+#define AIROHA_PCS_PMA_HEO_EMPHASIS BIT(16)
+#define AIROHA_PCS_PMA_A_MGAIN BIT(8)
+#define AIROHA_PCS_PMA_A_LGAIN BIT(0)
#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120
#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16)
#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8)
#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FEOS 0x144
+#define AIROHA_PCS_PMA_EQ_FORCE_BLWC_FREEZE BIT(8)
+#define AIROHA_PCS_PMA_LFSEL GENMASK(7, 0)
+#define AIROHA_PCS_PMA_SS_RX_BLWC 0x148
+#define AIROHA_PCS_PMA_EQ_BLWC_CNT_BOT_LIM GENMASK(29, 23)
+#define AIROHA_PCS_PMA_EQ_BLWC_CNT_TOP_LIM GENMASK(22, 16)
+#define AIROHA_PCS_PMA_EQ_BLWC_GAIN GENMASK(11, 8)
+#define AIROHA_PCS_PMA_EQ_BLWC_POL BIT(0)
+#define AIROHA_PCS_PMA_EQ_BLWC_POL_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x0)
+#define AIROHA_PCS_PMA_EQ_BLWC_POL_INVERSION FIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x1)
#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c
#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16)
#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0)
@@ -1022,31 +1208,182 @@
#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_RX_PI_CAL 0x15c
+#define AIROHA_PCS_PMA_KPGAIN GENMASK(10, 8)
+#define AIROHA_PCS_PMA_RX_CAL1 0x160
+#define AIROHA_PCS_PMA_CAL_CYC GENMASK(25, 24)
+#define AIROHA_PCS_PMA_CAL_CYC_63 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x0)
+#define AIROHA_PCS_PMA_CAL_CYC_15 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x1)
+#define AIROHA_PCS_PMA_CAL_CYC_31 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x2)
+#define AIROHA_PCS_PMA_CAL_CYC_127 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x3)
+#define AIROHA_PCS_PMA_CAL_STB GENMASK(17, 16)
+#define AIROHA_PCS_PMA_CAL_STB_5US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x0)
+#define AIROHA_PCS_PMA_CAL_STB_8US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x1)
+#define AIROHA_PCS_PMA_CAL_STB_16US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x2)
+#define AIROHA_PCS_PMA_CAL_STB_32US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x3)
+#define AIROHA_PCS_PMA_CAL_1US_SET GENMASK(15, 8)
+#define AIROHA_PCS_PMA_SIM_FAST_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_CAL2 0x164
+#define AIROHA_PCS_PMA_CAL_CYC_TIME GENMASK(17, 16)
+#define AIROHA_PCS_PMA_CAL_OUT_OS GENMASK(11, 8)
+#define AIROHA_PCS_PMA_CAL_OS_PULSE BIT(0)
#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c
#define AIROHA_PCS_PMA_SIGDET_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_0 0x170
+#define AIROHA_PCS_PMA_KBAND_KFC GENMASK(25, 24)
+#define AIROHA_PCS_PMA_KBAND_KFC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x0)
+#define AIROHA_PCS_PMA_KBAND_KFC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x1)
+#define AIROHA_PCS_PMA_KBAND_KFC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x2)
+#define AIROHA_PCS_PMA_KBAND_KFC_64 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x3)
+#define AIROHA_PCS_PMA_FPKDIV GENMASK(18, 8)
+#define AIROHA_PCS_PMA_KBAND_PREDIV GENMASK(2, 0)
+#define AIROHA_PCS_PMA_KBAND_PREDIV_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x0)
+#define AIROHA_PCS_PMA_KBAND_PREDIV_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x1)
+#define AIROHA_PCS_PMA_KBAND_PREDIV_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x2)
+#define AIROHA_PCS_PMA_KBAND_PREDIV_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x3)
#define AIROHA_PCS_PMA_RX_FLL_1 0x174
+#define AIROHA_PCS_PMA_SYMBOL_WD GENMASK(26, 24)
+#define AIROHA_PCS_PMA_SETTLE_TIME_SEL GENMASK(18, 16)
#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0)
#define AIROHA_PCS_PMA_RX_FLL_2 0x178
#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16)
#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_AMP GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PRBS_SEL GENMASK(2, 0)
#define AIROHA_PCS_PMA_RX_FLL_5 0x184
#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16)
#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_6 0x188
+#define AIROHA_PCS_PMA_LNX_SW_FLL_4_LATCH_EN BIT(24)
+#define AIROHA_PCS_PMA_LNX_SW_FLL_3_LATCH_EN BIT(16)
+#define AIROHA_PCS_PMA_LNX_SW_FLL_2_LATCH_EN BIT(8)
+#define AIROHA_PCS_PMA_LNX_SW_FLL_1_LATCH_EN BIT(0)
#define AIROHA_PCS_PMA_RX_FLL_B 0x19c
#define AIROHA_PCS_PMA_LOAD_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_PDOS_CTRL_0 0x200
+#define AIROHA_PCS_PMA_SAP_SEL GENMASK(18, 16)
+#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x0)
+#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x1)
+#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x2)
+#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x3)
+#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x4)
+#define AIROHA_PCS_PMA_EYE_BLWC_ADD BIT(8)
+#define AIROHA_PCS_PMA_DATA_BLWC_ADD BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_0 0x204
+#define AIROHA_PCS_PMA_CAL_RST_B BIT(24)
+#define AIROHA_PCS_PMA_EQ_PI_CAL_RST_B BIT(16)
+#define AIROHA_PCS_PMA_FEOS_RST_B BIT(8)
#define AIROHA_PCS_PMA_RX_RESET_1 0x208
#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8)
+#define AIROHA_PCS_PMA_PDOS_RST_B BIT(0)
+#define AIROHA_PCS_PMA_RX_DEBUG_0 0x20c
+#define AIROHA_PCS_PMA_RO_TOGGLE BIT(24)
+#define AIROHA_PCS_PMA_BISTCTL_CONTROL 0x210
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL GENMASK(4, 0)
+/* AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x0) */
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x1)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x2)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS15 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x3)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS23 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x4)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS31 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x5)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_HFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x6)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_MFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x7)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x8)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_5_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x9)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xa)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xb)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_8_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xc)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xd)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xe)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xf)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PROG_80 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x10)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x11)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x12)
+#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x13)
+#define AIROHA_PCS_PMA_BISTCTL_ALIGN_PAT 0x214
+#define AIROHA_PCS_PMA_BISTCTL_POLLUTION 0x220
+#define AIROHA_PCS_PMA_BIST_TX_DATA_POLLUTION_LATCH BIT(16)
+#define AIROHA_PCS_PMA_BISTCTL_PRBS_INITIAL_SEED 0x224
+#define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD 0x230
+#define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD_MASK GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_2 0x23c
+#define AIROHA_PCS_PMA_PI_CAL_DATA_OUT GENMASK(22, 16)
+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_5 0x248
+#define AIROHA_PCS_PMA_VEO_RDY BIT(24)
+#define AIROHA_PCS_PMA_HEO_RDY BIT(16)
+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_9 0x258
+#define AIROHA_PCS_PMA_EO_Y_DONE BIT(24)
+#define AIROHA_PCS_PMA_EO_X_DONE BIT(16)
+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_10 0x25c
+#define AIROHA_PCS_PMA_EYE_EL GENMASK(26, 16)
+#define AIROHA_PCS_PMA_EYE_ER GENMASK(10, 0)
#define AIROHA_PCS_PMA_TX_RST_B 0x260
#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8)
#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0)
+#define AIROHA_PCS_PMA_TX_CALIB_0 0x264
+#define AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL GENMASK(25, 24)
+#define AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL_EN BIT(16)
+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_11 0x290
+#define AIROHA_PCS_PMA_EYE_EB GENMASK(14, 8)
+#define AIROHA_PCS_PMA_EYE_EU GENMASK(6, 0)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_0 0x294
+#define AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_0 0x300
+#define AIROHA_PCS_PMA_DISB_DA_XPON_CDR_LPF_RSTB BIT(24)
+#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_GAIN_CTRL BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_1 0x304
+#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E0 BIT(24)
+#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D1 BIT(16)
+#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D0 BIT(8)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_2 0x308
+#define AIROHA_PCS_PMA_DISB_DA_XPON_CDR_PR_PIEYE BIT(24)
+#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_VOS BIT(16)
+#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_EYE BIT(8)
+#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E1 BIT(0)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_3 0x30c
+#define AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY BIT(0)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_6 0x318
+#define AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_EYECNT_RDY BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_3 0x31c
+#define AIROHA_PCS_PMA_DISB_RQ_PI_CAL_RDY BIT(0)
#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320
#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_5 0x324
+#define AIROHA_PCS_PMA_DISB_RX_OR_PICAL_EN BIT(24)
+#define AIROHA_PCS_PMA_DISB_EYECNT_RDY BIT(16)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_7 0x328
+#define AIROHA_PCS_PMA_FORCE_PDOS_RX_RST_B BIT(16)
+#define AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB BIT(0)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_8 0x32c
+#define AIROHA_PCS_PMA_FORCE_EYECNT_RX_RST_B BIT(24)
+#define AIROHA_PCS_PMA_FORCE_FEOS_RX_RST_B BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SDCAL_REF_RST_B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_BLWC_RX_RST_B BIT(0)
#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330
+#define AIROHA_PCS_PMA_FORCE_EYE_TOP_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O BIT(8)
#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_6 0x334
+#define AIROHA_PCS_PMA_DISB_PDOS_RX_RST_B BIT(16)
+#define AIROHA_PCS_PMA_DISB_RX_AND_PICAL_RSTB BIT(8)
+#define AIROHA_PCS_PMA_DISB_REF_AND_PICAL_RSTB BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_7 0x338
+#define AIROHA_PCS_PMA_DISB_EYECNT_RX_RST_B BIT(24)
+#define AIROHA_PCS_PMA_DISB_FEOS_RX_RST_B BIT(16)
+#define AIROHA_PCS_PMA_DISB_SDCAL_REF_RST_B BIT(8)
+#define AIROHA_PCS_PMA_DISB_BLWC_RX_RST_B BIT(0)
#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c
+#define AIROHA_PCS_PMA_DISB_EYE_TOP_EN BIT(16)
+#define AIROHA_PCS_PMA_DISB_EYE_RESET_PLU_O BIT(8)
#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_SS_BIST_1 0x344
+#define AIROHA_PCS_PMA_LNX_BISTCTL_BIT_ERROR_RST_SEL BIT(24)
+#define AIROHA_PCS_PMA_ANLT_PX_LNX_LT_LOS BIT(0)
#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c
#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24)
#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16)
@@ -1069,7 +1406,11 @@
#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0)
#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c
#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_ADD_CLKPATH_RST_0 0x410
+#define AIROHA_PCS_PMA_CLKPATH_RSTB_CK BIT(8)
+#define AIROHA_PCS_PMA_CLKPATH_RST_EN BIT(0)
#define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414
+#define AIROHA_PCS_PMA_TX_BIST_GEN_EN BIT(16)
#define AIROHA_PCS_PMA_XFI_RX_MODE GENMASK(11, 9)
#define AIROHA_PCS_PMA_XFI_RX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x0)
#define AIROHA_PCS_PMA_XFI_RX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x1)
@@ -1085,7 +1426,26 @@
#define AIROHA_PCS_PMA_XFI_TX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x3)
#define AIROHA_PCS_PMA_XFI_TX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x4)
#define AIROHA_PCS_PMA_XFI_TX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x5)
+#define AIROHA_PCS_PMA_ADD_RX2ANA_1 0x424
+#define AIROHA_PCS_PMA_RX_DAC_E0 GENMASK(30, 24)
+#define AIROHA_PCS_PMA_RX_DAC_D1 GENMASK(22, 16)
+#define AIROHA_PCS_PMA_RX_DAC_D0 GENMASK(14, 8)
+#define AIROHA_PCS_PMA_RX_DAC_EYE GENMASK(6, 0)
+#define AIROHA_PCS_PMA_ADD_RX2ANA_2 0x428
+#define AIROHA_PCS_PMA_RX_FEOS_OUT GENMASK(13, 8)
+#define AIROHA_PCS_PMA_RX_DAC_E1 GENMASK(6, 0)
+#define AIROHA_PCS_PMA_PON_TX_COUNTER_0 0x440
+#define AIROHA_PCS_PMA_TXCALIB_5US GENMASK(31, 16)
+#define AIROHA_PCS_PMA_TXCALIB_50US GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PON_TX_COUNTER_1 0x444
+#define AIROHA_PCS_PMA_TX_HSDATA_EN_WAIT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_TX_CK_EN_WAIT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PON_TX_COUNTER_2 0x448
+#define AIROHA_PCS_PMA_TX_SERDES_RDY_WAIT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_TX_POWER_ON_WAIT GENMASK(15, 0)
#define AIROHA_PCS_PMA_SW_RST_SET 0x460
+#define AIROHA_PCS_PMA_SW_XFI_RXMAC_RST_N BIT(17)
+#define AIROHA_PCS_PMA_SW_XFI_TXMAC_RST_N BIT(16)
#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11)
#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10)
#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)
@@ -1098,17 +1458,32 @@
#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2)
#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1)
#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0)
+#define AIROHA_PCS_PMA_TX_DLY_CTRL 0x468
+#define AIROHA_PCS_PMA_OUTBEN_DATA_MODE GENMASK(30, 28)
+#define AIROHA_PCS_PMA_TX_BEN_EXTEN_FTUNE GENMASK(23, 16)
+#define AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE GENMASK(14, 8)
+#define AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE GENMASK(6, 0)
#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474
#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16)
#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c
#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16)
#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
+/* 4ref_ck step:
+ * - 0x1 4ref_ck
+ * - 0x2 8ref_ck
+ * - 0x3 12ref_ck
+ * ...
+ */
+#define AIROHA_PCS_PMA_L2D_TRIG_EQ_EN_TIME GENMASK(15, 8)
+#define AIROHA_PCS_PMA_OS_RDY_LATCH BIT(1)
#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
#define AIROHA_PCS_PMA_RX_FREQDET 0x530
#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16)
#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0)
#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580
#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_MD32_MEM_CLK_CTRL 0x60c
+#define AIROHA_PCS_PMA_MD32PM_CK_SEL GENMASK(31, 0)
#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768
#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)
#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)
@@ -1131,8 +1506,13 @@
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0)
#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE GENMASK(22, 16)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_FLL_COR 0x790
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_DAC_EYE BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_DAC_EYE GENMASK(22, 16)
#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
@@ -1152,6 +1532,9 @@
#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814
#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_EN 0x808
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_AEQ_EN BIT(0)
#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818
#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16)
@@ -1177,6 +1560,14 @@
#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN_RSTB 0x83c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_CKON BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_CKON BIT(16)
+#define AIROHA_PCS_PMA_PXP_RX_OSCAL_EN 0x840
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_EN BIT(0)
#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c
#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
@@ -1187,6 +1578,12 @@
#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_KBAND_LOAD_EN 0x858
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_KBAND_LOAD_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_KBAND_LOAD_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW_CHG 0x864
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW_CHG BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW_CHG BIT(0)
#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16)
@@ -1198,6 +1595,14 @@
#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SIGDET_CAL_EN 0x898
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_CAL_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_CAL_EN BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_12 0x8b8
+#define AIROHA_PCS_PMA_RESERVE_12_FEOS_0 BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_24 0x8fc
+#define AIROHA_PCS_PMA_FORCE_RX_GEARBOX BIT(12)
+#define AIROHA_PCS_PMA_FORCE_SEL_RX_GEARBOX BIT(8)
#define AIROHA_PCS_PMA_DIG_RESERVE_29 0x910
#define AIROHA_PCS_PMA_2L_TX_RATE_CTRL GENMASK(1, 0)
#define AIROHA_PCS_PMA_2L_RX_RATE_CTRL GENMASK(5, 4)
@@ -1207,6 +1612,19 @@
#define AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT 4
#define AIROHA_PCS_MAX_NUM_RSTS 2
+enum pon_eo_buf_vals {
+ EYE_EU,
+ EYE_EB,
+ DAC_D0,
+ DAC_D1,
+ DAC_E0,
+ DAC_E1,
+ DAC_EYE,
+ FEOS,
+
+ EO_BUF_MAX,
+};
+
enum xfi_port_type {
AIROHA_PCS_ETH,
AIROHA_PCS_PON,
@@ -1256,6 +1674,11 @@ struct airoha_pcs_match_data {
int num_port;
enum xfi_port_type port_type;
+ bool hibernation_workaround;
+ bool usxgmii_ber_time_fixup;
+ bool usxgmii_rx_gb_out_vld_tweak;
+ bool usxgmii_xfi_mode_sel;
+
int (*alloc_regmap_fields)(struct airoha_pcs_priv *priv);
int (*bringup)(struct airoha_pcs_priv *priv,
int index, phy_interface_t interface);
@@ -1309,3 +1732,30 @@ static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv,
return 0;
}
#endif
+
+#ifdef CONFIG_PCS_AIROHA_AN7583
+int an7583_pcs_common_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+
+int an7583_pcs_usb_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+
+void an7583_pcs_common_phya_link_up(struct airoha_pcs_priv *priv, int index);
+#else
+static inline int an7583_pcs_common_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7583_pcs_usb_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void an7583_pcs_common_phya_link_up(struct airoha_pcs_priv *priv,
+ int index)
+{
+}
+#endif
diff --git a/drivers/net/pcs/airoha/pcs-an7583.c b/drivers/net/pcs/airoha/pcs-an7583.c
new file mode 100644
index 000000000000..42e8a00889af
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-an7583.c
@@ -0,0 +1,2349 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/regmap.h>
+
+#include "pcs-airoha.h"
+
+static void an7583_pcs_dig_reset_hold(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_PMA_RST_N);
+
+ usleep_range(50, 100);
+}
+
+static void an7583_pcs_dig_reset_release(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_PMA_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N);
+
+ usleep_range(100, 200);
+}
+
+static void an7583_pcs_common_phya_txpll(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 pcw, tdc_pcw;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII: /* DS(RX)_1.25G / US(TX)_1.25G*/
+ case PHY_INTERFACE_MODE_1000BASEX:
+ pcw = 0x32000000;
+ tdc_pcw = 0x64000000;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX: /* DS(RX)_3.125G / US(TX)_3.125G */
+ pcw = 0x3e800000;
+ tdc_pcw = 0x7d000000;
+ break;
+ case PHY_INTERFACE_MODE_5GBASER: /* DS(RX)_5.15625G / US(TX)_5.15625G */
+ case PHY_INTERFACE_MODE_USXGMII: /* DS(RX)_10.31252G / US(TX)_10.3125G */
+ case PHY_INTERFACE_MODE_10GBASER:
+ pcw = 0x33900000;
+ tdc_pcw = 0x67200000;
+ break;
+ default:
+ return;
+ }
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_FLT_3,
+ AIROHA_PCS_PMA_LCPLL_NCPO_LOAD);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_PCW_1,
+ AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON,
+ FIELD_PREP(AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON,
+ tdc_pcw));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_PCW_2,
+ AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_EPON,
+ FIELD_PREP(AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_EPON,
+ tdc_pcw));
+}
+
+static void an7583_pcs_common_phya_tx(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 fir_cn1, fir_c0b, fir_c1, fir_c2;
+ u32 tx_ben_exten_ftune;
+ u32 tx_dly_data_ftune;
+ u32 tx_dly_ben_ftune;
+ u32 ckin_divisor;
+ u32 tx_rate_ctrl;
+
+ if (data->port_type == AIROHA_PCS_ETH ||
+ data->port_type == AIROHA_PCS_PON ||
+ data->port_type == AIROHA_PCS_PCIE)
+ tx_ben_exten_ftune = 0x2;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ ckin_divisor = BIT(1);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 8;
+ fir_c1 = 0;
+ fir_c2 = 0;
+
+ if (data->port_type == AIROHA_PCS_PON) {
+ tx_ben_exten_ftune = 0x7;
+ tx_dly_ben_ftune = 0x2;
+ tx_dly_data_ftune = 0x6;
+ }
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ ckin_divisor = BIT(2);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 8;
+ fir_c1 = 1;
+ fir_c2 = 0;
+ if (data->port_type == AIROHA_PCS_PON)
+ tx_ben_exten_ftune = 0x2;
+ break;
+ case PHY_INTERFACE_MODE_5GBASER:
+ ckin_divisor = BIT(2);
+ tx_rate_ctrl = BIT(1);
+ fir_cn1 = 0;
+ fir_c0b = 14;
+ fir_c1 = 4;
+ fir_c2 = 0;
+ if (data->port_type == AIROHA_PCS_PON)
+ tx_ben_exten_ftune = 0x2;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ ckin_divisor = BIT(2) | BIT(0);
+ tx_rate_ctrl = BIT(1);
+ fir_cn1 = 0;
+ fir_c0b = 14;
+ fir_c1 = 4;
+ fir_c2 = 0;
+
+ if (data->port_type == AIROHA_PCS_PON) {
+ tx_ben_exten_ftune = 0x16;
+ tx_dly_ben_ftune = 0xd;
+ tx_dly_data_ftune = 0x30;
+ }
+
+ break;
+ default:
+ return;
+ }
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN,
+ AIROHA_PCS_ANA_TX_DMEDGEGEN_EN |
+ AIROHA_PCS_ANA_TX_CKLDO_EN);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CMN_EN,
+ AIROHA_PCS_ANA_CMN_VREFSEL |
+ AIROHA_PCS_ANA_CMN_MPXSELTOP_DC |
+ AIROHA_PCS_ANA_CMN_EN,
+ AIROHA_PCS_ANA_CMN_VREFSEL_9V |
+ FIELD_PREP(AIROHA_PCS_ANA_CMN_MPXSELTOP_DC, 0x1) |
+ AIROHA_PCS_ANA_CMN_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2, fir_c2) |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+ ckin_divisor));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ tx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ tx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_TX_DLY_CTRL,
+ AIROHA_PCS_PMA_TX_BEN_EXTEN_FTUNE,
+ FIELD_PREP(AIROHA_PCS_PMA_TX_BEN_EXTEN_FTUNE, tx_ben_exten_ftune));
+
+ if (data->port_type == AIROHA_PCS_PON) {
+ if (interface == PHY_INTERFACE_MODE_SGMII || interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_USXGMII || interface == PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_TX_DLY_CTRL,
+ AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE |
+ AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE,
+ FIELD_PREP(AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE, tx_dly_ben_ftune) |
+ FIELD_PREP(AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE, tx_dly_data_ftune));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_MD32_MEM_CLK_CTRL,
+ AIROHA_PCS_PMA_MD32PM_CK_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_MD32PM_CK_SEL, 0x3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_TX_DLY_CTRL,
+ AIROHA_PCS_PMA_OUTBEN_DATA_MODE,
+ FIELD_PREP(AIROHA_PCS_PMA_OUTBEN_DATA_MODE, 0x1));
+ }
+}
+
+static void an7583_pcs_common_phya_rx(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 cdr_pr_beta_dac;
+ u32 rx_force_mode_0;
+ u32 dig_reserve_0;
+ u32 rx_rate_ctrl;
+ u32 fe_gain_ctrl;
+ u32 busbit_sel;
+ u32 phyck_sel;
+ u32 phyck_div;
+ u32 lpf_ratio;
+ u32 rx_rev0;
+ u32 osr;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ dig_reserve_0 = 0x300;
+ cdr_pr_beta_dac = 0x8;
+ phyck_sel = 0x1;
+ phyck_div = 0x29;
+ lpf_ratio = 0x3;
+ osr = 0x3;
+ rx_rate_ctrl = 0x0;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ dig_reserve_0 = 0x300;
+ cdr_pr_beta_dac = 0x6;
+ phyck_sel = 0x1;
+ phyck_div = 0xb;
+ lpf_ratio = 0x1;
+ osr = 0x1;
+ rx_rate_ctrl = 0x0;
+ break;
+ case PHY_INTERFACE_MODE_5GBASER:
+ dig_reserve_0 = 0x400;
+ cdr_pr_beta_dac = 0x8;
+ phyck_sel = 0x2;
+ phyck_div = 0x42;
+ lpf_ratio = 0x1;
+ osr = 0x1;
+ rx_rate_ctrl = 0x2;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ dig_reserve_0 = 0x100;
+ cdr_pr_beta_dac = 0x8;
+ phyck_sel = 0x2;
+ phyck_div = 0x42;
+ lpf_ratio = 0x0;
+ osr = 0x0;
+ rx_rate_ctrl = 0x2;
+ break;
+ default:
+ return;
+ }
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_REV_0,
+ AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL |
+ AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL |
+ AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK,
+ FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) |
+ FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) |
+ FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW,
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_OSCAL_FORCE,
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS));
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+ AIROHA_PCS_ANA_CDR_PD_EDGE_DIS |
+ AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_12,
+ AIROHA_PCS_PMA_RESERVE_12_FEOS_0);
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ rx_rev0 = FIELD_PREP(AIROHA_PCS_ANA_REV_0_FE_BUF2_BIAS_TYPE, 0x1) |
+ FIELD_PREP(AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_NORMAL, 0x3);
+ fe_gain_ctrl = 0x1;
+ rx_force_mode_0 = 0x1;
+ } else {
+ rx_rev0 = FIELD_PREP(AIROHA_PCS_ANA_REV_0_FE_BUF2_BIAS_TYPE, 0x1) |
+ AIROHA_PCS_ANA_REV_0_OSCAL_FE_MODE_SET_SEL |
+ BIT(7) | /* FIXME: Missing documentation for this BIT */
+ FIELD_PREP(AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_NORMAL, 0x3);
+ fe_gain_ctrl = 0x3;
+ rx_force_mode_0 = 0x3;
+ }
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_REV_0,
+ AIROHA_PCS_ANA_RX_REV_0, rx_rev0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ fe_gain_ctrl));
+
+ regmap_write(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_0,
+ dig_reserve_0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_0,
+ AIROHA_PCS_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL,
+ rx_force_mode_0));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_0,
+ AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_GAIN_CTRL);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC,
+ AIROHA_PCS_ANA_CDR_PR_BETA_DAC,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC,
+ cdr_pr_beta_dac));
+
+ if (data->port_type == AIROHA_PCS_ETH &&
+ interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(priv->pcs_ana,
+ AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,
+ AIROHA_PCS_ANA_CDR_PR_DAC_BAND,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_DAC_BAND,
+ 0x6));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,
+ AIROHA_PCS_ANA_RX_PHYCK_SEL,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel));
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+ AIROHA_PCS_ANA_CDR_PR_XFICK_EN);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL,
+ AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE |
+ AIROHA_PCS_ANA_RX_PHY_CK_SEL,
+ AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,
+ AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+ AIROHA_PCS_ANA_RX_PHYCK_DIV,
+ AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+ FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,
+ AIROHA_PCS_ANA_CDR_LPF_RATIO,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO,
+ lpf_ratio));
+
+ if (interface == PHY_INTERFACE_MODE_5GBASER)
+ busbit_sel = AIROHA_PCS_ANA_RX_BUSBIT_SEL_FORCE |
+ AIROHA_PCS_ANA_RX_BUSBIT_SEL_16BIT;
+ else
+ busbit_sel = 0;
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL,
+ AIROHA_PCS_ANA_RX_BUSBIT_SEL_FORCE |
+ AIROHA_PCS_ANA_RX_BUSBIT_SEL,
+ busbit_sel);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+ AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl));
+}
+
+static void an7583_pcs_common_phya_ana(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 lpf_br, lpf_bwr;
+ u32 txpll_chp_ibias;
+ bool chp_double_en;
+ u32 tcl_amp_vref;
+ bool sdm_hren;
+ bool sdm_ifm;
+ u32 vco_cfix;
+ bool sdm_di;
+ bool vcodiv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ if (data->port_type == AIROHA_PCS_PON) {
+ txpll_chp_ibias = 0x18;
+ lpf_br = 0xa;
+ lpf_bwr = 0x16;
+ } else {
+ txpll_chp_ibias = 0x31;
+ lpf_br = 0x5;
+ lpf_bwr = 0xb;
+ }
+ vco_cfix = 0x3;
+ tcl_amp_vref = 0xb;
+ vcodiv = false;
+ sdm_hren = data->port_type == AIROHA_PCS_PON;
+ sdm_ifm = data->port_type == AIROHA_PCS_PON;
+ sdm_di = data->port_type == AIROHA_PCS_PON;
+ chp_double_en = false;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ txpll_chp_ibias = 0x1e;
+ if (data->port_type == AIROHA_PCS_PCIE) {
+ lpf_br = 0xa;
+ lpf_bwr = 0x16;
+ } else {
+ lpf_br = 0x5;
+ lpf_bwr = 0xb;
+ }
+ vco_cfix = 0x0;
+ tcl_amp_vref = 0xe;
+ vcodiv = true;
+ sdm_hren = false;
+ sdm_ifm = false;
+ sdm_di = false;
+ chp_double_en = data->port_type == AIROHA_PCS_PON ||
+ data->port_type == AIROHA_PCS_PCIE;
+ break;
+ case PHY_INTERFACE_MODE_5GBASER:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ txpll_chp_ibias = 0x18;
+ lpf_br = 0xa;
+ lpf_bwr = 0x16;
+ sdm_hren = true;
+ vco_cfix = 0x2;
+ tcl_amp_vref = 0xb;
+ vcodiv = false;
+ sdm_ifm = true;
+ sdm_di = true;
+ chp_double_en = false;
+ break;
+ default:
+ return;
+ }
+
+ if (data->port_type == AIROHA_PCS_PON ||
+ data->port_type == AIROHA_PCS_PCIE)
+ /* XPON TDC */
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_PLL_MONCLK_SEL,
+ AIROHA_PCS_ANA_TDC_AUTOEN);
+
+ /* TXPLL VCO LDO Out */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+ AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT |
+ AIROHA_PCS_ANA_TXPLL_LDO_OUT,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_VTP_EN,
+ AIROHA_PCS_ANA_TXPLL_VTP |
+ AIROHA_PCS_ANA_TXPLL_VTP_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VTP, 0x0) |
+ AIROHA_PCS_ANA_TXPLL_VTP_EN);
+
+ if (data->port_type == AIROHA_PCS_ETH ||
+ data->port_type == AIROHA_PCS_PON)
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TDC_SYNC_CK_SEL,
+ AIROHA_PCS_ANA_PLL_LDO_CKDRV_VSEL |
+ AIROHA_PCS_ANA_PLL_LDO_CKDRV_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_PLL_LDO_CKDRV_VSEL, 0x1) |
+ AIROHA_PCS_ANA_PLL_LDO_CKDRV_EN);
+
+ /* Setup RSTB */
+ /* FIXME: different order */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL,
+ AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+ AIROHA_PCS_ANA_TXPLL_RST_DLY |
+ AIROHA_PCS_ANA_TXPLL_REFIN_DIV |
+ AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL,
+ AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_REFIN_DIV,
+ AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1));
+
+ /* Setup SDM */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN,
+ AIROHA_PCS_ANA_TXPLL_SDM_MODE |
+ AIROHA_PCS_ANA_TXPLL_SDM_IFM |
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_LS |
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) |
+ (sdm_ifm ? AIROHA_PCS_ANA_TXPLL_SDM_IFM : 0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS,
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23) |
+ (sdm_di ? AIROHA_PCS_ANA_TXPLL_SDM_DI_EN : 0));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+ AIROHA_PCS_ANA_TXPLL_SDM_HREN |
+ AIROHA_PCS_ANA_TXPLL_SDM_OUT |
+ AIROHA_PCS_ANA_TXPLL_SDM_ORD,
+ (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_ORD,
+ AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM));
+
+ /* Setup SSC */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1,
+ AIROHA_PCS_ANA_TXPLL_SSC_DELTA |
+ AIROHA_PCS_ANA_TXPLL_SSC_DELTA1,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0));
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN,
+ AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN |
+ AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI |
+ AIROHA_PCS_ANA_TXPLL_SSC_EN);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+ AIROHA_PCS_ANA_TXPLL_SSC_PERIOD,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0));
+
+ regmap_update_bits(priv->pcs_ana, AN7583_PCS_ANA_PXP_TXPLL_CHP_DOUBLE_EN,
+ AIROHA_PCS_ANA_TXPLL_SPARE_L,
+ chp_double_en ? AIROHA_PCS_ANA_TXPLL_SPARE_L : 0);
+
+ /* Setup LPF */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS,
+ AIROHA_PCS_ANA_TXPLL_LPF_BC |
+ AIROHA_PCS_ANA_TXPLL_LPF_BR |
+ AIROHA_PCS_ANA_TXPLL_CHP_IOFST |
+ AIROHA_PCS_ANA_TXPLL_CHP_IBIAS,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, lpf_br) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, txpll_chp_ibias));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+ AIROHA_PCS_ANA_TXPLL_LPF_BWC |
+ AIROHA_PCS_ANA_TXPLL_LPF_BWR |
+ AIROHA_PCS_ANA_TXPLL_LPF_BP,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, 0x18) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, 0x2));
+
+ /* Setup VCO */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+ AIROHA_PCS_ANA_TXPLL_VCO_CFIX,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN,
+ AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L |
+ AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H |
+ AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR |
+ AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR |
+ AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) |
+ AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN);
+
+ /* Setup KBand */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE,
+ AIROHA_PCS_ANA_TXPLL_KBAND_KF |
+ AIROHA_PCS_ANA_TXPLL_KBAND_KFC |
+ AIROHA_PCS_ANA_TXPLL_KBAND_DIV |
+ AIROHA_PCS_ANA_TXPLL_KBAND_CODE,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x2) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+ AIROHA_PCS_ANA_TXPLL_KBAND_KS,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1));
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+ AIROHA_PCS_ANA_TXPLL_KBAND_OPTION);
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+ AIROHA_PCS_ANA_TXPLL_VCO_KBAND_MEAS_EN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_KBAND_LOAD_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_KBAND_LOAD_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_KBAND_LOAD_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_KBAND_LOAD_EN);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+ AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE |
+ AIROHA_PCS_ANA_TXPLL_POSTDIV_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE,
+ AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2) |
+ AIROHA_PCS_ANA_TXPLL_POSTDIV_EN);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN,
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF |
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN,
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4));
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+ AIROHA_PCS_ANA_TXPLL_POSTDIV_D256_EN);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+ AIROHA_PCS_ANA_TXPLL_VCODIV,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCODIV,
+ vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+ AIROHA_PCS_ANA_TXPLL_VCODIV_1));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+ AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW |
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW,
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5) |
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN);
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN);
+
+ /* Setup TX TermCal */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TX_TXLBRC_EN,
+ AIROHA_PCS_ANA_TX_TERMCAL_VREF_L |
+ AIROHA_PCS_ANA_TX_TERMCAL_VREF_H,
+ FIELD_PREP(AIROHA_PCS_ANA_TX_TERMCAL_VREF_L, 0x2) |
+ FIELD_PREP(AIROHA_PCS_ANA_TX_TERMCAL_VREF_H, 0x2));
+
+ /* Setup XPON RX */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN,
+ AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+ AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+ AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN |
+ AIROHA_PCS_ANA_RX_FE_EQ_HZEN,
+ AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+ AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+ AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN);
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB,
+ AIROHA_PCS_ANA_RX_FE_VCM_GEN_PWDB);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,
+ AIROHA_PCS_ANA_CDR_LPF_TOP_LIM,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x8000));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_BOT_LIM,
+ AIROHA_PCS_ANA_CDR_LPF_BOT_LIM,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_BOT_LIM, 0x78000));
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PR_CKREF_DIV,
+ AIROHA_PCS_ANA_CDR_PR_RSTB_BYPASS);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE,
+ AIROHA_PCS_ANA_RX_DAC_RANGE_EYE,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_RANGE_EYE, 0x2));
+}
+
+static void an7583_pcs_cfg_phy_type(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+ if (data->port_type == AIROHA_PCS_PON ||
+ data->port_type == AIROHA_PCS_PCIE) {
+ /* TDC */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_FLT_3,
+ AIROHA_PCS_PMA_LCPLL_NCPO_SHIFT,
+ FIELD_PREP(AIROHA_PCS_PMA_LCPLL_NCPO_SHIFT, 0x1));
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_FLT_1,
+ AIROHA_PCS_PMA_LCPLL_A_TDC,
+ FIELD_PREP(AIROHA_PCS_PMA_LCPLL_A_TDC, 0x5));
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TX_TERMCAL_SELPN,
+ AIROHA_PCS_ANA_TX_TDC_CK_SEL,
+ FIELD_PREP(AIROHA_PCS_ANA_TX_TDC_CK_SEL, 0x0));
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,
+ AIROHA_PCS_ANA_RX_TDC_CK_SEL);
+ }
+
+ /* PLL EN HW Mode */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+ AIROHA_PCS_PMA_LCPLL_CK_STB_TIMER |
+ AIROHA_PCS_PMA_LCPLL_PCW_MAN_LOAD_TIMER |
+ AIROHA_PCS_PMA_LCPLL_EN_TIMER |
+ AIROHA_PCS_PMA_LCPLL_MAN_PWDB,
+ FIELD_PREP(AIROHA_PCS_PMA_LCPLL_CK_STB_TIMER, 0x1) |
+ FIELD_PREP(AIROHA_PCS_PMA_LCPLL_PCW_MAN_LOAD_TIMER, 0x10) |
+ FIELD_PREP(AIROHA_PCS_PMA_LCPLL_EN_TIMER, 0xa) |
+ AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PON_TX_COUNTER_1,
+ AIROHA_PCS_PMA_TX_HSDATA_EN_WAIT |
+ AIROHA_PCS_PMA_TX_CK_EN_WAIT,
+ FIELD_PREP(AIROHA_PCS_PMA_TX_HSDATA_EN_WAIT, 0x113) |
+ FIELD_PREP(AIROHA_PCS_PMA_TX_CK_EN_WAIT, 0xfa));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PON_TX_COUNTER_2,
+ AIROHA_PCS_PMA_TX_SERDES_RDY_WAIT |
+ AIROHA_PCS_PMA_TX_POWER_ON_WAIT,
+ FIELD_PREP(AIROHA_PCS_PMA_TX_SERDES_RDY_WAIT, 0x9b) |
+ FIELD_PREP(AIROHA_PCS_PMA_TX_POWER_ON_WAIT, 0x210));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PON_TX_COUNTER_0,
+ AIROHA_PCS_PMA_TXCALIB_5US |
+ AIROHA_PCS_PMA_TXCALIB_50US,
+ FIELD_PREP(AIROHA_PCS_PMA_TXCALIB_5US, 0x4) |
+ FIELD_PREP(AIROHA_PCS_PMA_TXCALIB_50US, 0x26));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_FLT_0,
+ AIROHA_PCS_PMA_LCPLL_KI,
+ FIELD_PREP(AIROHA_PCS_PMA_LCPLL_KI, 0x3));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_PW_5,
+ AIROHA_PCS_PMA_LCPLL_TDC_SYNC_IN_MODE);
+
+ an7583_pcs_common_phya_txpll(priv, index, interface);
+ an7583_pcs_common_phya_tx(priv, index, interface);
+
+ /* RX HW mode counter */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+ AIROHA_PCS_PMA_RX_OS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+ AIROHA_PCS_PMA_RX_OS_END,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+ AIROHA_PCS_PMA_OSC_SPEED_OPT,
+ AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+ AIROHA_PCS_PMA_RX_PICAL_END |
+ AIROHA_PCS_PMA_RX_PICAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x3e8) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+ AIROHA_PCS_PMA_RX_SDCAL_END |
+ AIROHA_PCS_PMA_RX_SDCAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x3e8) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+ AIROHA_PCS_PMA_RX_PDOS_END |
+ AIROHA_PCS_PMA_RX_PDOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x3e8) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+ AIROHA_PCS_PMA_RX_FEOS_END |
+ AIROHA_PCS_PMA_RX_FEOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x3e8) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+ /* RX Settings */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,
+ AIROHA_PCS_PMA_FOM_NUM_ORDER |
+ AIROHA_PCS_PMA_A_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+ FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_0,
+ AIROHA_PCS_PMA_X_MAX | AIROHA_PCS_PMA_X_MIN,
+ FIELD_PREP(AIROHA_PCS_PMA_X_MAX, 0x240) |
+ FIELD_PREP(AIROHA_PCS_PMA_X_MIN, 0x1c0));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+ AIROHA_PCS_PMA_DATA_SHIFT);
+
+ an7583_pcs_common_phya_rx(priv, index, interface);
+ an7583_pcs_common_phya_ana(priv, index, interface);
+
+ /* Setup EYE */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+ AIROHA_PCS_PMA_EYECNT_FAST);
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_3,
+ AIROHA_PCS_PMA_EYE_NEXTPTS);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_0,
+ AIROHA_PCS_PMA_EYECNT_VTH |
+ AIROHA_PCS_PMA_EYECNT_HTH,
+ FIELD_PREP(AIROHA_PCS_PMA_EYECNT_VTH, 0x4) |
+ FIELD_PREP(AIROHA_PCS_PMA_EYECNT_HTH, 0x4));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_1,
+ AIROHA_PCS_PMA_EO_VTH |
+ AIROHA_PCS_PMA_EO_HTH,
+ FIELD_PREP(AIROHA_PCS_PMA_EO_VTH, 0x4) |
+ FIELD_PREP(AIROHA_PCS_PMA_EO_HTH, 0x4));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0,
+ AIROHA_PCS_PMA_EYE_MASK |
+ AIROHA_PCS_PMA_CNTLEN,
+ FIELD_PREP(AIROHA_PCS_PMA_EYE_MASK, 0xff) |
+ FIELD_PREP(AIROHA_PCS_PMA_CNTLEN, 0xd0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_0,
+ AIROHA_PCS_PMA_VEO_MASK |
+ AIROHA_PCS_PMA_HEO_MASK |
+ AIROHA_PCS_PMA_EQ_EN_DELAY,
+ FIELD_PREP(AIROHA_PCS_PMA_VEO_MASK, 0x0) |
+ FIELD_PREP(AIROHA_PCS_PMA_HEO_MASK, 0x0) |
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_EN_DELAY, 0x1));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_1,
+ AIROHA_PCS_PMA_A_LGAIN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CAL1,
+ AIROHA_PCS_PMA_CAL_CYC |
+ AIROHA_PCS_PMA_CAL_STB |
+ AIROHA_PCS_PMA_CAL_1US_SET |
+ AIROHA_PCS_PMA_SIM_FAST_EN,
+ AIROHA_PCS_PMA_CAL_CYC_15 |
+ AIROHA_PCS_PMA_CAL_STB_8US |
+ FIELD_PREP(AIROHA_PCS_PMA_CAL_1US_SET, 0x2e) |
+ AIROHA_PCS_PMA_SIM_FAST_EN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CAL2,
+ AIROHA_PCS_PMA_CAL_CYC_TIME |
+ AIROHA_PCS_PMA_CAL_OUT_OS |
+ AIROHA_PCS_PMA_CAL_OS_PULSE,
+ FIELD_PREP(AIROHA_PCS_PMA_CAL_CYC_TIME, 0x0) |
+ FIELD_PREP(AIROHA_PCS_PMA_CAL_OUT_OS, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+ AIROHA_PCS_PMA_RX_RDY |
+ AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FEOS,
+ AIROHA_PCS_PMA_EQ_FORCE_BLWC_FREEZE |
+ AIROHA_PCS_PMA_LFSEL,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_FORCE_BLWC_FREEZE, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_1,
+ AIROHA_PCS_PMA_INDEX_MODE |
+ AIROHA_PCS_PMA_Y_MAX |
+ AIROHA_PCS_PMA_Y_MIN,
+ AIROHA_PCS_PMA_INDEX_MODE |
+ FIELD_PREP(AIROHA_PCS_PMA_Y_MAX, 0x3f) |
+ FIELD_PREP(AIROHA_PCS_PMA_Y_MIN, 0x40));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_2,
+ AIROHA_PCS_PMA_EYEDUR,
+ FIELD_PREP(AIROHA_PCS_PMA_EYEDUR, 0x18));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+ AIROHA_PCS_PMA_L2D_TRIG_EQ_EN_TIME |
+ AIROHA_PCS_PMA_OS_RDY_LATCH |
+ AIROHA_PCS_PMA_DISB_LEQ,
+ FIELD_PREP(AIROHA_PCS_PMA_L2D_TRIG_EQ_EN_TIME, 0x2) |
+ AIROHA_PCS_PMA_OS_RDY_LATCH);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_0,
+ AIROHA_PCS_PMA_KBAND_KFC |
+ AIROHA_PCS_PMA_FPKDIV,
+ AIROHA_PCS_PMA_KBAND_KFC_8 |
+ FIELD_PREP(AIROHA_PCS_PMA_FPKDIV, 0xa5));
+
+ if (data->port_type == AIROHA_PCS_PCIE)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_0,
+ AIROHA_PCS_PMA_KBAND_PREDIV,
+ AIROHA_PCS_PMA_KBAND_PREDIV_8);
+ else
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_0,
+ AIROHA_PCS_PMA_KBAND_PREDIV,
+ AIROHA_PCS_PMA_KBAND_PREDIV_4);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_1,
+ AIROHA_PCS_PMA_SYMBOL_WD |
+ AIROHA_PCS_PMA_SETTLE_TIME_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_SYMBOL_WD, 0x4) |
+ FIELD_PREP(AIROHA_PCS_PMA_SETTLE_TIME_SEL, 0x1));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_5,
+ AIROHA_PCS_PMA_FLL_IDAC_MIN |
+ AIROHA_PCS_PMA_FLL_IDAC_MAX,
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x1ff));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_2,
+ AIROHA_PCS_PMA_AMP |
+ AIROHA_PCS_PMA_PRBS_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_AMP, 0x4) |
+ FIELD_PREP(AIROHA_PCS_PMA_PRBS_SEL, 0x3));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+ AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_PDOS_CTRL_0,
+ AIROHA_PCS_PMA_EYE_BLWC_ADD |
+ AIROHA_PCS_PMA_DATA_BLWC_ADD,
+ AIROHA_PCS_PMA_DATA_BLWC_ADD);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_BLWC,
+ AIROHA_PCS_PMA_EQ_BLWC_CNT_BOT_LIM |
+ AIROHA_PCS_PMA_EQ_BLWC_CNT_TOP_LIM |
+ AIROHA_PCS_PMA_EQ_BLWC_GAIN |
+ AIROHA_PCS_PMA_EQ_BLWC_POL,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_BLWC_CNT_BOT_LIM, 0x10) |
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_BLWC_CNT_TOP_LIM, 0x70) |
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_BLWC_GAIN, 0xa) |
+ AIROHA_PCS_PMA_EQ_BLWC_POL_INVERSION);
+}
+
+static void an7583_pcs_common_phya_txpll_on(struct airoha_pcs_priv *priv,
+ int index)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ if (data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+ AIROHA_PCS_ANA_JCPLL_SPARE_L,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SPARE_L,
+ AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+ }
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+ AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+ udelay(6);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+ AIROHA_PCS_ANA_TXPLL_FREQ_MEAS_EN |
+ AIROHA_PCS_ANA_TXPLL_VREF_SEL,
+ AIROHA_PCS_ANA_TXPLL_FREQ_MEAS_EN |
+ AIROHA_PCS_ANA_TXPLL_VREF_SEL_VBG);
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_PHY_CK1_EN,
+ AIROHA_PCS_ANA_TXPLL_PHY_CK2_EN |
+ AIROHA_PCS_ANA_TXPLL_PHY_CK1_EN);
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+ AIROHA_PCS_ANA_TXPLL_FREQ_MEAS_EN);
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_JCPLL_FREQ_MEAS_EN,
+ AIROHA_PCS_ANA_TXPLL_IB_EXT_EN);
+
+ if (data->port_type == AIROHA_PCS_PCIE)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+ AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+ AIROHA_PCS_PMA_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, 0x7fff) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, 0x7fff));
+
+ usleep_range(500, 1000);
+}
+
+static void an7583_pcs_common_phya_tx_on(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 xfi_tx_term_sel = 0x1;
+ // int efuse_valid;
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B,
+ AIROHA_PCS_PMA_TX_TOP_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_ADD_CLKPATH_RST_0,
+ AIROHA_PCS_PMA_CLKPATH_RSTB_CK |
+ AIROHA_PCS_PMA_CLKPATH_RST_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B,
+ AIROHA_PCS_PMA_TXCALIB_RST_B |
+ AIROHA_PCS_PMA_TX_TOP_RST_B);
+
+ usleep_range(100, 200);
+
+ /* TODO handle efuse */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_TX_CALIB_0,
+ AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL |
+ AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL_EN,
+ FIELD_PREP(AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL,
+ xfi_tx_term_sel) |
+ AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL_EN);
+}
+
+static void an7583_pcs_common_phya_rx_preset(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 cdr_pr_buf_in_sr;
+ bool cdr_pr_cap_en;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_2500BASEX:
+ if (data->port_type == AIROHA_PCS_PCIE) {
+ cdr_pr_cap_en = false;
+ cdr_pr_buf_in_sr = 0x7;
+ } else {
+ cdr_pr_cap_en = true;
+ cdr_pr_buf_in_sr = 0x6;
+ }
+
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_5GBASER:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ cdr_pr_cap_en = false;
+ cdr_pr_buf_in_sr = 0x7;
+ break;
+ default:
+ return;
+ }
+
+ /* Setup RX Precondition */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+ AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL |
+ AIROHA_PCS_ANA_RX_SIGDET_PEAK,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, 0x2) |
+ FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, 0x2));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE,
+ AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, 0x3));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+ AIROHA_PCS_ANA_CDR_PR_CAP_EN |
+ AIROHA_PCS_ANA_CDR_BUF_IN_SR,
+ (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_OS_RDY);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_OS_RDY);
+
+ /* Setup L2R */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+ /* Setup LEQ setting */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0));
+
+ /* Keep EYE reset */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_EYE_RESET_PLU_O);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_EYE_TOP_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_EYE_TOP_EN);
+
+ /* Kepp BLWC reset */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_7,
+ AIROHA_PCS_PMA_DISB_BLWC_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_BLWC_RX_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_BLWC_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_BLWC_EN);
+}
+
+static void an7583_pcs_common_phya_rx_on(struct airoha_pcs_priv *priv,
+ int index)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+ /* RX SigDet Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+ AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,
+ AIROHA_PCS_ANA_CDR_PR_FBKSEL |
+ AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL |
+ AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x5) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x5));
+
+ if (data->port_type == AIROHA_PCS_PCIE)
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,
+ AIROHA_PCS_ANA_CDR_PR_DAC_BAND,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_DAC_BAND, 0x8));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_PDOS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_FEOS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_SDCAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_OS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_BLWC_EN);
+
+ if (data->port_type == AIROHA_PCS_PCIE)
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_PMA_PXP_AEQ_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_EN |
+ AIROHA_PCS_PMA_FORCE_DA_AEQ_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_EN);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PR_CKREF_DIV,
+ AIROHA_PCS_ANA_CDR_PR_CKREF_DIV,
+ AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_1);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_PR_TDC_REF_SEL,
+ AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1,
+ AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_RX_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+ usleep_range(100, 200);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+}
+
+static void an7583_pcs_common_phya_l2d(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Setup LPF L2D force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+ usleep_range(200, 300);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+}
+
+static void an7583_pcs_common_phya_tdc_off(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_FLT_3,
+ AIROHA_PCS_PMA_LCPLL_NCPO_LOAD);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW_CHG,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW_CHG);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW_CHG,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW_CHG);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW_CHG,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW_CHG);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_FLT_1,
+ AIROHA_PCS_PMA_LCPLL_GPON_SEL,
+ AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_EPON);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_LCPLL_TDC_PW_0,
+ AIROHA_PCS_PMA_LCPLL_TDC_DIG_PWDB);
+
+ usleep_range(100, 200);
+}
+
+static void an7583_pcs_common_phya_rx_oscal(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_CKON |
+ AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_CKON);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_OSCAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_RSTB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_OSCAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_EN);
+
+ usleep_range(200, 300);
+
+ /* Set normal of force mode */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_OS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_OS_RDY);
+
+ /* Disable force mode signal */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_OS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_OS_RDY);
+
+ /* Release reset enable */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_OS_EN);
+}
+
+static void an7583_pcs_common_phya_pical(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Pre Condition */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_2,
+ AIROHA_PCS_PMA_DISB_DA_XPON_CDR_PR_PIEYE);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_PI_CAL,
+ AIROHA_PCS_PMA_KPGAIN,
+ FIELD_PREP(AIROHA_PCS_PMA_KPGAIN, 0x4));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_0,
+ AIROHA_PCS_PMA_EQ_EN_DELAY,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_EN_DELAY, 0x8));
+
+ /* Reset Block */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_0,
+ AIROHA_PCS_PMA_EQ_PI_CAL_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_6,
+ AIROHA_PCS_PMA_DISB_RX_AND_PICAL_RSTB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_6,
+ AIROHA_PCS_PMA_DISB_REF_AND_PICAL_RSTB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_3,
+ AIROHA_PCS_PMA_DISB_RQ_PI_CAL_RDY);
+
+ /* Enable */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_6,
+ AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_5,
+ AIROHA_PCS_PMA_DISB_RX_OR_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_3,
+ AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY);
+
+ /* Release Reset and Enable */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_0,
+ AIROHA_PCS_PMA_EQ_PI_CAL_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_6,
+ AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_PICAL_EN);
+
+ usleep_range(200, 300);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_6,
+ AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_3,
+ AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY);
+}
+
+static void an7583_pcs_common_phya_pdos(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN);
+
+ /* Pre Condition */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_OS_RDY);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_OS_RDY);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_1,
+ AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E0);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_1,
+ AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_1,
+ AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D0);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_2,
+ AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_2,
+ AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_EYE);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_BLWC_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_7,
+ AIROHA_PCS_PMA_DISB_BLWC_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_EYEDUR_INIT_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_DISB_EYEDUR_INIT_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_EYECNT_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_7,
+ AIROHA_PCS_PMA_DISB_EYECNT_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_EYEDUR_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_DISB_EYEDUR_EN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_PDOS_CTRL_0,
+ AIROHA_PCS_PMA_SAP_SEL,
+ AIROHA_PCS_PMA_SAP_SEL_SHIFT_8);
+
+ /* Reset Block */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_PDOS_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_6,
+ AIROHA_PCS_PMA_DISB_PDOS_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_1,
+ AIROHA_PCS_PMA_PDOS_RST_B);
+
+ /* Disable */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_PDOS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_PDOS_EN);
+
+ /* Release Reset and Enable */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_OS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_OS_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_PDOS_RX_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_1,
+ AIROHA_PCS_PMA_PDOS_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_PDOS_EN);
+
+ usleep_range(200, 300);
+
+ /* Disable (again) */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_PDOS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_OS_EN);
+
+ /* Release EYE related */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_EYEDUR_INIT_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_DISB_EYEDUR_INIT_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_EYECNT_RX_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_7,
+ AIROHA_PCS_PMA_DISB_EYECNT_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_EYEDUR_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_DISB_EYEDUR_EN);
+
+ /* Disable PDOS */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN);
+}
+
+static void an7583_pcs_common_phya_feos(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Pre Condition */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_OS_RDY);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_OS_RDY);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_2,
+ AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_VOS);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_BLWC_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_7,
+ AIROHA_PCS_PMA_DISB_BLWC_RX_RST_B);
+
+ /* Setting */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FEOS,
+ AIROHA_PCS_PMA_LFSEL,
+ FIELD_PREP(AIROHA_PCS_PMA_LFSEL, 0x30));
+
+ /* Reset */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_FEOS_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_7,
+ AIROHA_PCS_PMA_DISB_FEOS_RX_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_0,
+ AIROHA_PCS_PMA_FEOS_RST_B);
+
+ /* Disable */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_FEOS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_FEOS_EN);
+
+ /* Release Reset and Enable */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_OS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_OS_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_FEOS_RX_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_0,
+ AIROHA_PCS_PMA_FEOS_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_FEOS_EN);
+
+ usleep_range(1000, 1500);
+
+ /* Disable */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_FEOS_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_OS_EN);
+}
+
+static void an7583_pcs_common_phya_sdcal(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Pre Condition */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SIGDET_CAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_CAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_CAL_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_OSCAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_EN);
+
+ /* Reset */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_0,
+ AIROHA_PCS_PMA_CAL_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_SDCAL_REF_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_SDCAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_7,
+ AIROHA_PCS_PMA_DISB_SDCAL_REF_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_SDCAL_EN);
+
+ /* Release Reset and Enable */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_0,
+ AIROHA_PCS_PMA_CAL_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_8,
+ AIROHA_PCS_PMA_FORCE_SDCAL_REF_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_SDCAL_EN);
+
+ usleep_range(200, 300);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_SDCAL_EN);
+
+ /* SigDet Cal Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SIGDET_CAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_CAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_CAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_CAL_EN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_CKON |
+ AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_CKON,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_CKON);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_OSCAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_RSTB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_OSCAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN);
+}
+
+static void an7583_pcs_common_phya_phy_status(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_OS_RDY);
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_OS_RDY);
+ udelay(1);
+}
+
+static void an7583_pcs_common_phya_eye_setting(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 cdr_lpf_ratio;
+ u32 x_min, x_max;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ x_min = 0x0;
+ x_max = 0x400;
+ cdr_lpf_ratio = 0x3;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ x_min = 0x140;
+ x_max = 0x2c0;
+ cdr_lpf_ratio = 0x0;
+ break;
+ case PHY_INTERFACE_MODE_5GBASER:
+ x_min = 0x180;
+ x_max = 0x280;
+ cdr_lpf_ratio = 0x1;
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ x_min = 0x1c0;
+ x_max = 0x234;
+ cdr_lpf_ratio = 0x0;
+ break;
+ default:
+ return;
+ }
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,
+ AIROHA_PCS_ANA_CDR_LPF_RATIO,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO,
+ cdr_lpf_ratio));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0,
+ AIROHA_PCS_PMA_EYE_MASK,
+ FIELD_PREP(AIROHA_PCS_PMA_EYE_MASK, 0xff));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_0,
+ AIROHA_PCS_PMA_X_MAX | AIROHA_PCS_PMA_X_MIN,
+ FIELD_PREP(AIROHA_PCS_PMA_X_MAX, x_max) |
+ FIELD_PREP(AIROHA_PCS_PMA_X_MIN, x_min));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0,
+ AIROHA_PCS_PMA_CNTLEN,
+ FIELD_PREP(AIROHA_PCS_PMA_CNTLEN, 0xf8));
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0,
+ AIROHA_PCS_PMA_CNTFOREVER);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+ AIROHA_PCS_PMA_DATA_SHIFT);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_1,
+ AIROHA_PCS_PMA_INDEX_MODE);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_2,
+ AIROHA_PCS_PMA_EYEDUR,
+ FIELD_PREP(AIROHA_PCS_PMA_EYEDUR, 0x44c));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_3,
+ AIROHA_PCS_PMA_EYE_NEXTPTS |
+ AIROHA_PCS_PMA_EYE_NEXTPTS_TOGGLE |
+ AIROHA_PCS_PMA_EYE_NEXTPTS_SEL,
+ AIROHA_PCS_PMA_EYE_NEXTPTS);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_0,
+ AIROHA_PCS_PMA_EYECNT_VTH |
+ AIROHA_PCS_PMA_EYECNT_HTH,
+ FIELD_PREP(AIROHA_PCS_PMA_EYECNT_VTH, 0x4) |
+ FIELD_PREP(AIROHA_PCS_PMA_EYECNT_HTH, 0x4));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_1,
+ AIROHA_PCS_PMA_EO_VTH |
+ AIROHA_PCS_PMA_EO_HTH,
+ FIELD_PREP(AIROHA_PCS_PMA_EO_VTH, 0x4) |
+ FIELD_PREP(AIROHA_PCS_PMA_EO_HTH, 0x4));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_1,
+ AIROHA_PCS_PMA_B_ZERO_SEL |
+ AIROHA_PCS_PMA_HEO_EMPHASIS |
+ AIROHA_PCS_PMA_A_MGAIN |
+ AIROHA_PCS_PMA_A_LGAIN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,
+ AIROHA_PCS_PMA_A_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x1));
+}
+
+static void an7583_pcs_common_phya_eye_cal(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_FLL_COR,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_DAC_EYE |
+ AIROHA_PCS_PMA_FORCE_DA_RX_DAC_EYE,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_DAC_EYE, 0x0));
+
+ /* Redo PICal and reset Block */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_0,
+ AIROHA_PCS_PMA_EQ_EN_DELAY,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_EN_DELAY, 0x80));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_PI_CAL,
+ AIROHA_PCS_PMA_KPGAIN,
+ FIELD_PREP(AIROHA_PCS_PMA_KPGAIN, 0x1));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_0,
+ AIROHA_PCS_PMA_EQ_PI_CAL_RST_B);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_6,
+ AIROHA_PCS_PMA_DISB_RX_AND_PICAL_RSTB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_6,
+ AIROHA_PCS_PMA_DISB_REF_AND_PICAL_RSTB);
+
+ /* Enable PICal */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_5,
+ AIROHA_PCS_PMA_DISB_RX_OR_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_6,
+ AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0,
+ AIROHA_PCS_PMA_DISB_RX_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0,
+ AIROHA_PCS_PMA_FORCE_RX_PICAL_EN);
+
+ /* Release Reset */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_RESET_0,
+ AIROHA_PCS_PMA_EQ_PI_CAL_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_7,
+ AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_6,
+ AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN);
+
+ usleep_range(1000, 1500);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_6,
+ AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_3,
+ AIROHA_PCS_PMA_DISB_RQ_PI_CAL_RDY);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_3,
+ AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_5,
+ AIROHA_PCS_PMA_DISB_EYECNT_RDY);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_6,
+ AIROHA_PCS_PMA_FORCE_EYECNT_RDY);
+
+ usleep_range(1000, 1500);
+}
+
+static void an7583_pcs_common_phya_eye_eo_read(struct airoha_pcs_priv *priv,
+ int index, u32 *heo, u32 *veo)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 eo_buf[EO_BUF_MAX];
+ u32 eye_el, eye_er;
+ u32 feos;
+ u32 val;
+ int i;
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_6,
+ AIROHA_PCS_PMA_LNX_SW_FLL_4_LATCH_EN |
+ AIROHA_PCS_PMA_LNX_SW_FLL_3_LATCH_EN |
+ AIROHA_PCS_PMA_LNX_SW_FLL_2_LATCH_EN |
+ AIROHA_PCS_PMA_LNX_SW_FLL_1_LATCH_EN);
+
+ usleep_range(50, 100);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_6,
+ AIROHA_PCS_PMA_LNX_SW_FLL_4_LATCH_EN |
+ AIROHA_PCS_PMA_LNX_SW_FLL_3_LATCH_EN |
+ AIROHA_PCS_PMA_LNX_SW_FLL_2_LATCH_EN |
+ AIROHA_PCS_PMA_LNX_SW_FLL_1_LATCH_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DEBUG_0,
+ AIROHA_PCS_PMA_RO_TOGGLE);
+
+ usleep_range(100, 200);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DEBUG_0,
+ AIROHA_PCS_PMA_RO_TOGGLE);
+
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_TORGS_DEBUG_10, &val);
+ eye_el = FIELD_GET(AIROHA_PCS_PMA_EYE_EL, val);
+ eye_er = FIELD_GET(AIROHA_PCS_PMA_EYE_ER, val);
+
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_TORGS_DEBUG_11, &val);
+ eo_buf[EYE_EU] = FIELD_GET(AIROHA_PCS_PMA_EYE_EU, val);
+ eo_buf[EYE_EB] = FIELD_GET(AIROHA_PCS_PMA_EYE_EB, val);
+
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_ADD_RX2ANA_1, &val);
+ eo_buf[DAC_EYE] = FIELD_GET(AIROHA_PCS_PMA_RX_DAC_EYE, val);
+ eo_buf[DAC_D0] = FIELD_GET(AIROHA_PCS_PMA_RX_DAC_D0, val);
+ eo_buf[DAC_D1] = FIELD_GET(AIROHA_PCS_PMA_RX_DAC_D1, val);
+ eo_buf[DAC_E0] = FIELD_GET(AIROHA_PCS_PMA_RX_DAC_E0, val);
+
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_ADD_RX2ANA_2, &val);
+ eo_buf[FEOS] = FIELD_GET(AIROHA_PCS_PMA_RX_FEOS_OUT, val);
+ eo_buf[DAC_E1] = FIELD_GET(AIROHA_PCS_PMA_RX_DAC_E1, val);
+
+ feos = eo_buf[FEOS];
+
+ for (i = 0; i < ARRAY_SIZE(eo_buf); i++) {
+ if ((eo_buf[i] == feos) && (eo_buf[i] >= 32))
+ eo_buf[i] = eo_buf[i] - 64;
+ else if (eo_buf[i] >= 64)
+ eo_buf[i] = eo_buf[i] - 128;
+ }
+
+ /* Check if CLK unlocking happens (E0 result validity) */
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_TORGS_DEBUG_5, &val);
+ if (!FIELD_GET(AIROHA_PCS_PMA_HEO_RDY, val)) {
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_0,
+ AIROHA_PCS_PMA_DISB_DA_XPON_CDR_LPF_RSTB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_0,
+ AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB);
+
+ usleep_range(500, 700);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_0,
+ AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB);
+
+ usleep_range(500, 700);
+ }
+
+ *heo = abs(eye_er - eye_el);
+ *veo = abs(eo_buf[EYE_EU] - eo_buf[EYE_EB]);
+}
+
+static void an7583_pcs_common_phya_eye_eo(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface,
+ u32 *heo, u32 *veo)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_EYE_RESET_PLU_O);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_EYE_TOP_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_EYE_TOP_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_EYE_TOP_EN);
+
+ if (interface == PHY_INTERFACE_MODE_10GBASER ||
+ interface == PHY_INTERFACE_MODE_USXGMII)
+ usleep_range(5500, 6000);
+ else
+ msleep(55);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_2,
+ AIROHA_PCS_PMA_DISB_DA_XPON_CDR_PR_PIEYE |
+ AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_EYE);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_DISB_EYEDUR_INIT_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_7,
+ AIROHA_PCS_PMA_DISB_EYECNT_RX_RST_B);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1,
+ AIROHA_PCS_PMA_DISB_EYEDUR_EN);
+
+ an7583_pcs_common_phya_eye_eo_read(priv, index, heo, veo);
+
+ /* Clear Eye SW value */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_EYE_TOP_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_EYE_TOP_EN);
+
+ /* Reset PICal Rdy */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_3,
+ AIROHA_PCS_PMA_DISB_RQ_PI_CAL_RDY);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_3,
+ AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY);
+
+ /* Reset Eyecnt Rdy */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_5,
+ AIROHA_PCS_PMA_DISB_EYECNT_RDY);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_6,
+ AIROHA_PCS_PMA_FORCE_EYECNT_RDY);
+}
+
+static void an7583_pcs_common_phya_eo_scan(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 best_heo = 0, best_veo = 0;
+ u32 leq_gain, best_leq_gain;
+ u32 best_leq_peacking = 0;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ case PHY_INTERFACE_MODE_5GBASER:
+ leq_gain = 3;
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ leq_gain = 1;
+ break;
+ default:
+ return;
+ }
+
+ best_leq_gain = leq_gain;
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+ an7583_pcs_common_phya_eye_setting(priv, index, interface);
+
+ /* EYE Open */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_0,
+ AIROHA_PCS_PMA_EQ_EN_DELAY,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_EN_DELAY, 0x80));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_PI_CAL,
+ AIROHA_PCS_PMA_KPGAIN,
+ FIELD_PREP(AIROHA_PCS_PMA_KPGAIN, 0x4));
+
+ for (; leq_gain <= FIELD_MAX(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL); leq_gain++) {
+ u32 leq_peaking;
+ u32 heo, veo;
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, leq_gain));
+
+ for (leq_peaking = 0; leq_peaking <= FIELD_MAX(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL); leq_peaking++) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, leq_peaking));
+
+ usleep_range(500, 700);
+
+ an7583_pcs_common_phya_eye_cal(priv, index);
+ an7583_pcs_common_phya_eye_eo(priv, index, interface, &heo, &veo);
+
+ if (veo > 53 && best_veo > 53) {
+ if (heo > best_heo) {
+ best_heo = heo;
+ best_veo = veo;
+ best_leq_peacking = leq_peaking;
+ best_leq_gain = leq_gain;
+ } else if (heo == best_heo && veo > best_veo) {
+ best_heo = heo;
+ best_veo = veo;
+ best_leq_peacking = leq_peaking;
+ best_leq_gain = leq_gain;
+ }
+ } else {
+ if (veo > best_veo) {
+ best_heo = heo;
+ best_veo = veo;
+ best_leq_peacking = leq_peaking;
+ best_leq_gain = leq_gain;
+ }
+ }
+ }
+ }
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, best_leq_gain));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, best_leq_peacking));
+}
+
+static void an7583_pcs_common_phya_rxrdy(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 xfi_rx_term_sel = 0x1;
+ // int efuse_valid;
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_FORCE_RX_RDY);
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_RDY);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+ /* TODO HANDLE EFUSE */
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+ AIROHA_PCS_ANA_RX_FE_50OHMS_SEL,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_FE_50OHMS_SEL,
+ xfi_rx_term_sel));
+}
+
+static void an7583_pcs_common_phya_bist_setting(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_write(pcs_pma, AIROHA_PCS_PMA_BISTCTL_ALIGN_PAT,
+ 0x8ff1fd53);
+ regmap_write(pcs_pma, AIROHA_PCS_PMA_BISTCTL_PRBS_INITIAL_SEED,
+ 0xFF1FD53);
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD,
+ AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD_MASK,
+ FIELD_PREP(AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD_MASK, 0x1));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_BISTCTL_CONTROL,
+ AIROHA_PCS_PMA_BISTCTL_PAT_SEL,
+ AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS31);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_BISTCTL_POLLUTION,
+ AIROHA_PCS_PMA_BIST_TX_DATA_POLLUTION_LATCH);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_BIST_1,
+ AIROHA_PCS_PMA_LNX_BISTCTL_BIT_ERROR_RST_SEL |
+ AIROHA_PCS_PMA_ANLT_PX_LNX_LT_LOS);
+}
+
+static void an7583_pcs_first_plug_in(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ an7583_pcs_common_phya_rx_preset(priv, index, interface);
+ if (data->port_type == AIROHA_PCS_PON ||
+ data->port_type == AIROHA_PCS_PCIE)
+ an7583_pcs_common_phya_tdc_off(priv, index);
+ an7583_pcs_common_phya_rx_on(priv, index);
+ an7583_pcs_common_phya_l2d(priv, index);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ an7583_pcs_common_phya_rx_oscal(priv, index);
+ an7583_pcs_common_phya_pical(priv, index);
+ an7583_pcs_common_phya_pdos(priv, index);
+ an7583_pcs_common_phya_feos(priv, index);
+ an7583_pcs_common_phya_sdcal(priv, index);
+ an7583_pcs_common_phya_phy_status(priv, index);
+
+ an7583_pcs_dig_reset_release(priv, index);
+
+ an7583_pcs_common_phya_l2d(priv, index);
+
+ if (data->port_type == AIROHA_PCS_PON)
+ an7583_pcs_common_phya_eo_scan(priv, index, interface);
+ an7583_pcs_common_phya_rxrdy(priv, index);
+ if (data->port_type == AIROHA_PCS_PON ||
+ data->port_type == AIROHA_PCS_PCIE)
+ an7583_pcs_common_phya_bist_setting(priv, index);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_TX_BIST_GEN_EN |
+ AIROHA_PCS_PMA_R2T_MODE);
+}
+
+static void an7583_pcs_ana_reset_release(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_XFI_RXMAC_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXMAC_RST_N);
+}
+
+int an7583_pcs_usb_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_set_bits(maps->multi_sgmii,
+ AIROHA_PCS_MULTI_SGMII_MSG_RX_LIK_STS_1,
+ AIROHA_PCS_PAUSE_STS_P2 | AIROHA_PCS_PAUSE_STS_P1);
+
+ return phy_set_mode_ext(priv->phy, PHY_MODE_ETHERNET, interface);
+}
+
+int an7583_pcs_common_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ if (priv->phy)
+ return an7583_pcs_usb_phya_bringup(priv, index, interface);
+
+ an7583_pcs_dig_reset_hold(priv, index);
+
+ an7583_pcs_cfg_phy_type(priv, index, interface);
+
+ an7583_pcs_common_phya_txpll_on(priv, index);
+
+ an7583_pcs_common_phya_tx_on(priv, index);
+
+ an7583_pcs_first_plug_in(priv, index, interface);
+
+ an7583_pcs_ana_reset_release(priv, index);
+
+ return 0;
+}
+
+void an7583_pcs_common_phya_link_up(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ if (priv->phy)
+ return;
+
+ /* First CDR reset */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ usleep_range(700, 1000);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+ usleep_range(100, 200);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+ /* Then RX Rdy reset */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_RDY);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1,
+ AIROHA_PCS_PMA_DISB_RX_RDY);
+}
--
2.53.0
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2026-09-11 7:23 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-09-11 7:23 [RFC PATCH net-next] net: pcs: airoha: add support for Airoha AN7583 SoC Christian Marangi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®