From: Judith Mendez <jm@ti.com>
To: Judith Mendez <jm@ti.com>, Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW1 efuse node for silicon revision
Date: Mon, 14 Sep 2026 19:13:04 -0500 [thread overview]
Message-ID: <20260915001304.3781247-1-jm@ti.com> (raw)
Add efuse node for GP_SW1 register at offset 0x230. The GP_SW1
efuse register is used to determine AM62Px silicon revision.
Reference efuse cell from chipid node via nvmem-cells.
Signed-off-by: Judith Mendez <jm@ti.com>
---
.../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
index 8612b45e665cf..0f00e9d87f8ba 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
@@ -19,9 +19,23 @@ wkup_conf: bus@43000000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ nvmem-cells = <&gpsw1>;
+ nvmem-cell-names = "gpsw1";
bootph-all;
};
+ gpsw_efuse: efuse@230 {
+ compatible = "ti,am62p-efuse", "socionext,uniphier-efuse";
+ reg = <0x230 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ gpsw1: gpsw1@4 {
+ reg = <0x4 0x4>;
+ };
+ };
+
opp_efuse_table: syscon@18 {
compatible = "ti,am62-opp-efuse-table", "syscon";
reg = <0x18 0x4>;
--
2.34.1
next reply other threads:[~2026-09-15 0:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 0:13 Judith Mendez [this message]
2026-09-15 16:40 ` Kumar, Udit
2026-09-15 22:42 ` Judith Mendez
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