* [PATCH] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW1 efuse node for silicon revision
@ 2026-09-15 0:13 Judith Mendez
2026-09-15 16:40 ` Kumar, Udit
0 siblings, 1 reply; 3+ messages in thread
From: Judith Mendez @ 2026-09-15 0:13 UTC (permalink / raw)
To: Judith Mendez, Nishanth Menon
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel
Add efuse node for GP_SW1 register at offset 0x230. The GP_SW1
efuse register is used to determine AM62Px silicon revision.
Reference efuse cell from chipid node via nvmem-cells.
Signed-off-by: Judith Mendez <jm@ti.com>
---
.../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
index 8612b45e665cf..0f00e9d87f8ba 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
@@ -19,9 +19,23 @@ wkup_conf: bus@43000000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ nvmem-cells = <&gpsw1>;
+ nvmem-cell-names = "gpsw1";
bootph-all;
};
+ gpsw_efuse: efuse@230 {
+ compatible = "ti,am62p-efuse", "socionext,uniphier-efuse";
+ reg = <0x230 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ gpsw1: gpsw1@4 {
+ reg = <0x4 0x4>;
+ };
+ };
+
opp_efuse_table: syscon@18 {
compatible = "ti,am62-opp-efuse-table", "syscon";
reg = <0x18 0x4>;
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW1 efuse node for silicon revision
2026-09-15 0:13 [PATCH] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW1 efuse node for silicon revision Judith Mendez
@ 2026-09-15 16:40 ` Kumar, Udit
2026-09-15 22:42 ` Judith Mendez
0 siblings, 1 reply; 3+ messages in thread
From: Kumar, Udit @ 2026-09-15 16:40 UTC (permalink / raw)
To: Judith Mendez, Nishanth Menon
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel, u-kumar1
Hi Judith,
On 9/15/2026 5:43 AM, Judith Mendez wrote:
> Add efuse node for GP_SW1 register at offset 0x230. The GP_SW1
> efuse register is used to determine AM62Px silicon revision.
> Reference efuse cell from chipid node via nvmem-cells.
>
> Signed-off-by: Judith Mendez <jm@ti.com>
> ---
> .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> index 8612b45e665cf..0f00e9d87f8ba 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> @@ -19,9 +19,23 @@ wkup_conf: bus@43000000 {
> chipid: chipid@14 {
> compatible = "ti,am654-chipid";
> reg = <0x14 0x4>;
> + nvmem-cells = <&gpsw1>;
> + nvmem-cell-names = "gpsw1";
> bootph-all;
> };
>
> + gpsw_efuse: efuse@230 {
> + compatible = "ti,am62p-efuse", "socionext,uniphier-efuse";
> + reg = <0x230 0x10>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bootph-all;
> +
> + gpsw1: gpsw1@4 {
> + reg = <0x4 0x4>;
> + };
For J722S, this register this marked as reserved,
Could you update in am62-p specific dt.
Thanks
> + };
> +
> opp_efuse_table: syscon@18 {
> compatible = "ti,am62-opp-efuse-table", "syscon";
> reg = <0x18 0x4>;
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW1 efuse node for silicon revision
2026-09-15 16:40 ` Kumar, Udit
@ 2026-09-15 22:42 ` Judith Mendez
0 siblings, 0 replies; 3+ messages in thread
From: Judith Mendez @ 2026-09-15 22:42 UTC (permalink / raw)
To: Kumar, Udit, Nishanth Menon
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel
Hi Udit,
On 9/15/26 11:40 AM, Kumar, Udit wrote:
>
> Hi Judith,
>
> On 9/15/2026 5:43 AM, Judith Mendez wrote:
>> Add efuse node for GP_SW1 register at offset 0x230. The GP_SW1
>> efuse register is used to determine AM62Px silicon revision.
>> Reference efuse cell from chipid node via nvmem-cells.
>>
>> Signed-off-by: Judith Mendez <jm@ti.com>
>> ---
>> .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
>> index 8612b45e665cf..0f00e9d87f8ba 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
>> @@ -19,9 +19,23 @@ wkup_conf: bus@43000000 {
>> chipid: chipid@14 {
>> compatible = "ti,am654-chipid";
>> reg = <0x14 0x4>;
>> + nvmem-cells = <&gpsw1>;
>> + nvmem-cell-names = "gpsw1";
>> bootph-all;
>> };
>>
>> + gpsw_efuse: efuse@230 {
>> + compatible = "ti,am62p-efuse", "socionext,uniphier-efuse";
>> + reg = <0x230 0x10>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + bootph-all;
>> +
>> + gpsw1: gpsw1@4 {
>> + reg = <0x4 0x4>;
>> + };
>
> For J722S, this register this marked as reserved,
> Could you update in am62-p specific dt.
Right, let me see what I can do.
Thanks for reviewing.
~ Judith
>
> Thanks
>
>> + };
>> +
>> opp_efuse_table: syscon@18 {
>> compatible = "ti,am62-opp-efuse-table", "syscon";
>> reg = <0x18 0x4>;
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-09-15 22:43 UTC | newest]
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2026-09-15 0:13 [PATCH] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW1 efuse node for silicon revision Judith Mendez
2026-09-15 16:40 ` Kumar, Udit
2026-09-15 22:42 ` Judith Mendez
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