From: Borislav Petkov <bp@alien8.de>
To: "Naveen N Rao (AMD)" <naveen@kernel.org>,
Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>,
linux-kernel@vger.kernel.org, x86@kernel.org,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Bharata B Rao <bharata@amd.com>,
Manali Shukla <manali.shukla@amd.com>,
Nikunj A Dadhania <nikunj@amd.com>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH RESEND v4 0/3] x86/apic: Add support for additional AMD EILVT registers
Date: Mon, 14 Sep 2026 17:29:40 -0700 [thread overview]
Message-ID: <20260915002940.GDaqiRdNKYpyKgL2_B@fat_crate.local> (raw)
In-Reply-To: <cover.1788425679.git.naveen@kernel.org>
On Thu, Sep 03, 2026 at 02:58:38PM +0530, Naveen N Rao (AMD) wrote:
> Add support for additional APIC EILVT registers being introduced in
> future AMD processors:
> https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
>
> This is a resend of v4, rebased on tip/master. Previous posting:
> http://lore.kernel.org/r/cover.1784785046.git.naveen@kernel.org
>
> Since then:
> - I have retained the macro name 'APIC_EILVT_NR_AMD_10H' since I felt it
> is accurate, and didn't hear a preference for anything else. Happy to
> change if needed (Ingo)
> - I have gone through Sashiko's findings on the previous versions, and
> none of those justified a change. Other than the pre-existing issues
> reported by Sashiko, there have been 3 findings:
Except that someone should address the preexisting issues before we pile more
ontop:
https://sashiko.dev/#/patchset/cover.1788425679.git.naveen%40kernel.org
I see Ravi looks like the one who's been most busy here. CCed.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2026-09-15 0:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 9:28 Naveen N Rao (AMD)
2026-09-03 9:28 ` [PATCH RESEND v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Naveen N Rao (AMD)
2026-09-19 3:40 ` Borislav Petkov
2026-09-03 9:28 ` [PATCH RESEND v4 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Naveen N Rao (AMD)
2026-09-03 9:28 ` [PATCH RESEND v4 3/3] x86/apic: Drop APIC_EILVT_NR_MAX Naveen N Rao (AMD)
2026-09-07 5:16 ` [PATCH RESEND v4 0/3] x86/apic: Add support for additional AMD EILVT registers Bharata B Rao
2026-09-15 0:29 ` Borislav Petkov [this message]
2026-09-18 7:03 ` Ravi Bangoria
2026-09-19 1:46 ` Borislav Petkov
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