From: Orgad Shaneh <orgads@gmail.com>
To: tsbogend@alpha.franken.de
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 4/5] MIPS: OCTEON: program L2C_CTL, not L2C_CFG, on OCTEON II
Date: Tue, 15 Sep 2026 07:12:47 +0000 [thread overview]
Message-ID: <20260915071306.15006-4-orgads@gmail.com> (raw)
In-Reply-To: <20260915071306.15006-1-orgads@gmail.com>
cvmx_helper_initialize_packet_io_global() sets the L2 arbitration modes
by rewriting L2C_CFG. That register (0x1180080000000) does not exist on
OCTEON II; there the L2 controller is configured through L2C_CTL
(0x1180080800000), whose corresponding fields are rsp_arb_mode and
xmc_arb_mode.
On a CN6335 the stray write hung the board hard when this function ran -
no exception, no watchdog, just a dead console.
Keep the L2C_CFG write for CN3XXX/CN5XXX and program L2C_CTL on CN6XXX
with the values the vendor SDK uses there (rsp_arb_mode 1,
xmc_arb_mode 0), which is the same trade the existing code makes for
the older parts: keep IO blocks from being starved under high L2 load.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Orgad Shaneh <orgads@gmail.com>
---
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -1014,7 +1014,6 @@ int cvmx_helper_initialize_packet_io_global(void)
{
int result = 0;
int interface;
- union cvmx_l2c_cfg l2c_cfg;
const int num_interfaces = cvmx_helper_get_number_of_interfaces();
/*
@@ -1029,10 +1028,21 @@ int cvmx_helper_initialize_packet_io_global(void)
* to the cores. This avoids conditions where IO blocks might
* be starved under very high L2 loads.
*/
- l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
- l2c_cfg.s.lrf_arb_mode = 0;
- l2c_cfg.s.rfb_arb_mode = 0;
- cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ union cvmx_l2c_ctl l2c_ctl;
+
+ l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
+ l2c_ctl.s.rsp_arb_mode = 1;
+ l2c_ctl.s.xmc_arb_mode = 0;
+ cvmx_write_csr(CVMX_L2C_CTL, l2c_ctl.u64);
+ } else {
+ union cvmx_l2c_cfg l2c_cfg;
+
+ l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+ l2c_cfg.s.lrf_arb_mode = 0;
+ l2c_cfg.s.rfb_arb_mode = 0;
+ cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
+ }
cvmx_pko_initialize_global();
for (interface = 0; interface < num_interfaces; interface++) {
--
2.47.0
next prev parent reply other threads:[~2026-09-15 7:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 7:12 [PATCH 1/5] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX Orgad Shaneh
2026-09-15 7:12 ` [PATCH 2/5] MIPS: OCTEON: cvmx-l2c: add the CN66XX L2 geometry Orgad Shaneh
2026-09-15 7:12 ` [PATCH 3/5] MIPS: OCTEON: read the L2 crippled fuses from MIO_FUS_DAT3 on OCTEON II Orgad Shaneh
2026-09-15 7:12 ` Orgad Shaneh [this message]
2026-09-15 7:12 ` [PATCH 5/5] MIPS: OCTEON: require the Core-14449 workaround only on CN63XX pass 1 Orgad Shaneh
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