[PATCH 5/5] MIPS: OCTEON: require the Core-14449 workaround only on CN63XX pass 1

[Orgad Shaneh <orgads@gmail.com>]

prom_free_prom_memory() probes the hint field of a compiler-emitted
PREF and panics when it is not 28, which is what -Wa,-mfix-cn63xxp1
(CONFIG_CAVIUM_CN63XXP1) rewrites every prefetch in the kernel to. The
test is gated on OCTEON_IS_MODEL(OCTEON_CN6XXX), so it fires on every
OCTEON II part, including the pass 2 chips that do not need the
workaround:

  Kernel panic - not syncing: OCTEON II DCache prefetch workaround not
  in place (cfa00004).
  Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).

on a CN6335-AAP pass 2.2.

Core-14449 is a CN63XX pass 1.x erratum, and the vendor's own runtime
check says so: it errors out only for OCTEON_CN63XX_PASS1_X without the
fix, and otherwise merely warns about lost performance when fixed code
runs on a part that is not a CN63XX. Narrow the check to CN63XX pass
1.x to match.

The alternative - enabling CONFIG_CAVIUM_CN63XXP1 to satisfy the check -
is not free: the assembler flag rewrites every prefetch in the kernel
(77 of them in this build) to pref 0x1c, which is worth avoiding on an
in-order core whose receive path is dominated by memcpy.

uasm_i_pref() keeps its OCTEON_CN6XXX condition: it only touches the
handful of runtime-generated TLB handlers, where the cost does not
matter.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Orgad Shaneh <orgads@gmail.com>
---
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -1127,7 +1127,7 @@ EXPORT_SYMBOL(prom_putchar);
 
 void __init prom_free_prom_memory(void)
 {
-	if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
 		/* Check for presence of Core-14449 fix.  */
 		u32 insn;
 		u32 *foo;
-- 
2.47.0