* [PATCH v4 1/4] KVM: TDX: Track configurable CPUID bits allowed by KVM
2026-09-17 7:25 [PATCH v4 0/4] KVM: TDX: Validate directly configurable CPUID bits Binbin Wu
@ 2026-09-17 7:25 ` Binbin Wu
2026-09-17 7:25 ` [PATCH v4 2/4] KVM: TDX: Report CORE_CAPABILITIES as configurable Binbin Wu
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Binbin Wu @ 2026-09-17 7:25 UTC (permalink / raw)
To: linux-kernel, kvm
Cc: seanjc, pbonzini, dave.hansen, andrew.cooper3, nik.borisov, kas,
rick.p.edgecombe, xiaoyao.li, chao.gao, tony.lindgren,
kishen.maloor, dedekind1, binbin.wu
Add tdx_cpu_cfg_caps[] to track the subset of TDX directly configurable
CPUID feature bits that KVM supports, and build the masks during TDX
hardware setup via tdx_initialize_cpu_cfg_caps().
The TDX module reports the CPUID bits that the VMM can directly configure
for a TD, but KVM cannot blindly expose all reported bits to userspace.
Certain features imply additional architectural state, e.g. one or more
MSRs, that KVM must explicitly manage across host/guest transitions to
prevent host state corruption. The existing hardcoded denylist cannot
account for new host state clobbering features introduced by future TDX
modules.
Except for a few fixed-1 bits required for basic TDX support, host state
clobbering features are either directly configurable or gated by TD
ATTRIBUTES/XFAM, which KVM already validates. Tracking only the directly
configurable bits to build an allowlist is therefore sufficient.
Organize tdx_cpu_cfg_caps[] following kvm_cpu_caps[] so that the masks can
be built with similar feature-name based initializers. Directly
configurable non-feature bits will be handled separately.
The allowlist is prepared to be consumed by later patches to filter
KVM_TDX_CAPABILITIES and to reject unsupported CPUID input to
KVM_TDX_INIT_VM, so that newly introduced TDX directly configurable CPUID
feature bits stay hidden from userspace until KVM explicitly opts in.
By default, intersect the allowlist with kvm_cpu_caps[] via TDX_CFG_F().
Requiring support for non-TDX VMs avoids committing to TDX-specific
behavior before general KVM support is established, and respects KVM's
logic around disabling certain features, since the reasons for disabling
them could apply to TDX as well. Allow exceptions through
TDX_CFG_EXTRA_F() only with sufficient justification.
Add comments as placeholders for HLE, RTM, WAITPKG and FRED, which KVM
doesn't support for TDX yet.
Allow MWAIT, XTPR, and HT through TDX_CFG_EXTRA_F(), as these bits are
not advertised in kvm_cpu_caps[]. The remaining directly configurable
feature bits outside kvm_cpu_caps[] are left out of the allowlist:
- Features forced to zero when #VE is reduced, or lacking KVM support
for the associated MSRs: EST, TM2, SDBG, DCA, ACPI, ACC (TM), RDT_A,
RDT_M, TME, PCONFIG, and CORE_CAPABILITIES. Handle CORE_CAPABILITIES
in a subsequent patch.
- Features tied to IA32_MISC_ENABLE bits that a TD cannot set when
TDCS.TD_CTLS.REDUCE_VE is set: CID and PBE.
- Features that can clobber host state and lack KVM support for TDX:
FRED.
- Unsupported features: PREFETCHWT1 (Xeon Phi only), PSN (absent from
TDX-capable CPUs), AMX-TRANSPOSE (never implemented on an Intel
platform), and RAO_INT (defined only for future processors).
Filtering KVM_TDX_CAPABILITIES in a subsequent patch will intentionally
stop advertising the excluded bits as configurable, as the corresponding
features are unsupported or cannot be properly virtualized.
Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
---
v4:
- Add XTPR and HT to the allowlist.
- Explain in the changelog why some directly configurable bits are not
added to the allowlist.
- Improve comments/changelog. (Xiaoyao)
- Fix the bug that AMX_COMPLEX should be added for CPUID_1E_1_EAX instead
of CPUID_7_1_EDX.
v3:
- Drop the new data structure in v2 and only track feature bits by
following the organization of kvm_cpu_caps[], handle non-feature
bits separately. (Sean)
- Use two versions of macros (TDX_CFG_F() vs. TDX_CFG_EXTRA_F()) to
distinguish whether a supported TDX configurable CPUID bit should be
checked against KVM's common cpu capabilities.
- Add AMX_COMPLEX since it has been defined in the CPUID virtualization doc.
---
arch/x86/kvm/vmx/tdx.c | 164 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 164 insertions(+)
diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c
index 8a3f88b79b83d..2b51a85c998e8 100644
--- a/arch/x86/kvm/vmx/tdx.c
+++ b/arch/x86/kvm/vmx/tdx.c
@@ -52,6 +52,168 @@
__TDX_BUG_ON(__err, #__fn, __kvm, ", " #a1 " 0x%llx, " #a2 ", 0x%llx, " #a3 " 0x%llx", \
a1, a2, a3)
+static u32 tdx_cpu_cfg_caps[NR_KVM_CPU_CAPS] __ro_after_init;
+static_assert(ARRAY_SIZE(tdx_cpu_cfg_caps) == ARRAY_SIZE(kvm_cpu_caps));
+
+#define TDX_VALIDATE_CPU_CAP_USAGE(name) \
+ BUILD_BUG_ON(__feature_leaf(X86_FEATURE_##name) != \
+ tdx_cpu_cap_init_in_progress)
+
+/* For a feature bit that needs to be cap'ed by kvm_cpu_caps[]. */
+#define TDX_CFG_F(name) \
+({ \
+ TDX_VALIDATE_CPU_CAP_USAGE(name); \
+ tdx_cfg_caps |= feature_bit(name); \
+})
+
+/*
+ * For a feature bit that KVM allows for TDX guests even though it isn't
+ * advertised through kvm_cpu_caps[], e.g. MWAIT. Use this version only when
+ * there is a justification.
+ */
+#define TDX_CFG_EXTRA_F(name) \
+({ \
+ TDX_VALIDATE_CPU_CAP_USAGE(name); \
+ tdx_cfg_caps_extra |= feature_bit(name); \
+})
+
+#define tdx_cpu_cfg_cap_init(leaf, feature_initializers...) \
+do { \
+ const u32 __maybe_unused tdx_cpu_cap_init_in_progress = leaf; \
+ u32 tdx_cfg_caps_extra = 0; \
+ u32 tdx_cfg_caps = 0; \
+ \
+ feature_initializers \
+ tdx_cpu_cfg_caps[leaf] = (tdx_cfg_caps & kvm_cpu_caps[leaf]) | \
+ tdx_cfg_caps_extra; \
+} while (0)
+
+/*
+ * Initialize tdx_cpu_cfg_caps[], the list of CPUID features that KVM
+ * supports for TDX guests. It covers only the directly configurable CPUID
+ * bits reported by the TDX module; features controlled by XFAM and
+ * ATTRIBUTES are handled separately.
+ */
+static void __init tdx_initialize_cpu_cfg_caps(void)
+{
+ tdx_cpu_cfg_cap_init(CPUID_1_ECX,
+ /*
+ * KVM allows userspace to enumerate MONITOR+MWAIT support to
+ * the guest, but the MWAIT feature flag is never advertised
+ * to userspace for non-TDX VMs.
+ */
+ TDX_CFG_EXTRA_F(MWAIT),
+ /*
+ * XTPR can be exposed to a TD, but it never takes effect in
+ * the underlying hardware when the TD changes
+ * IA32_MISC_ENABLE[23].
+ */
+ TDX_CFG_EXTRA_F(XTPR),
+ TDX_CFG_F(TSC_DEADLINE_TIMER),
+ TDX_CFG_F(AVX),
+ TDX_CFG_F(F16C),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_1_EDX,
+ TDX_CFG_F(MCE),
+ TDX_CFG_F(MTRR),
+ TDX_CFG_F(MCA),
+ TDX_CFG_F(SELFSNOOP),
+ /*
+ * HT is a topology enumeration bit that KVM doesn't care
+ * about, but userspace may want to expose it to the guests.
+ */
+ TDX_CFG_EXTRA_F(HT),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_7_0_EBX,
+ TDX_CFG_F(BMI1),
+ /* HLE */
+ TDX_CFG_F(BMI2),
+ TDX_CFG_F(ERMS),
+ /* RTM */
+ TDX_CFG_F(AVX512F),
+ TDX_CFG_F(AVX512DQ),
+ TDX_CFG_F(ADX),
+ TDX_CFG_F(AVX512IFMA),
+ TDX_CFG_F(AVX512PF),
+ TDX_CFG_F(AVX512ER),
+ TDX_CFG_F(AVX512CD),
+ TDX_CFG_F(AVX512BW),
+ TDX_CFG_F(AVX512VL),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_7_ECX,
+ TDX_CFG_F(UMIP),
+ /* WAITPKG */
+ TDX_CFG_F(AVX512_VBMI2),
+ TDX_CFG_F(GFNI),
+ TDX_CFG_F(VAES),
+ TDX_CFG_F(VPCLMULQDQ),
+ TDX_CFG_F(AVX512_VNNI),
+ TDX_CFG_F(AVX512_BITALG),
+ TDX_CFG_F(AVX512_VPOPCNTDQ),
+ TDX_CFG_F(LA57),
+ TDX_CFG_F(RDPID),
+ TDX_CFG_F(CLDEMOTE),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_7_EDX,
+ TDX_CFG_F(AVX512_4VNNIW),
+ TDX_CFG_F(AVX512_4FMAPS),
+ TDX_CFG_F(FSRM),
+ TDX_CFG_F(AVX512_VP2INTERSECT),
+ TDX_CFG_F(SERIALIZE),
+ TDX_CFG_F(TSXLDTRK),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_7_1_EAX,
+ TDX_CFG_F(SHA512),
+ TDX_CFG_F(SM3),
+ TDX_CFG_F(SM4),
+ TDX_CFG_F(AVX_VNNI),
+ TDX_CFG_F(AVX512_BF16),
+ TDX_CFG_F(CMPCCXADD),
+ TDX_CFG_F(FZRM),
+ TDX_CFG_F(FSRS),
+ TDX_CFG_F(FSRC),
+ /* FRED */
+ TDX_CFG_F(LKGS),
+ TDX_CFG_F(WRMSRNS),
+ TDX_CFG_F(AMX_FP16),
+ TDX_CFG_F(AVX_IFMA),
+ TDX_CFG_F(LAM),
+ TDX_CFG_F(MOVRS),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_7_1_EDX,
+ TDX_CFG_F(AVX_VNNI_INT8),
+ TDX_CFG_F(AVX_NE_CONVERT),
+ TDX_CFG_F(AVX_VNNI_INT16),
+ TDX_CFG_F(PREFETCHITI),
+ TDX_CFG_F(AVX10),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_7_2_EDX,
+ TDX_CFG_F(DDPD_U),
+ TDX_CFG_F(MCDT_NO),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_1E_1_EAX,
+ TDX_CFG_F(AMX_COMPLEX_ALIAS),
+ TDX_CFG_F(AMX_FP8),
+ TDX_CFG_F(AMX_TF32),
+ TDX_CFG_F(AMX_AVX512),
+ TDX_CFG_F(AMX_MOVRS),
+ );
+
+ tdx_cpu_cfg_cap_init(CPUID_8000_0008_EBX,
+ TDX_CFG_F(WBNOINVD),
+ );
+}
+
+#undef TDX_CFG_F
+#undef TDX_CFG_EXTRA_F
bool enable_tdx __ro_after_init;
module_param_named(tdx, enable_tdx, bool, 0444);
@@ -3487,6 +3649,8 @@ int __init tdx_hardware_setup(void)
return r;
}
+ tdx_initialize_cpu_cfg_caps();
+
KVM_SANITY_CHECK_VM_STRUCT_SIZE(kvm_tdx);
vt_x86_ops.vm_size = max_t(unsigned int, vt_x86_ops.vm_size, sizeof(struct kvm_tdx));
--
2.46.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v4 2/4] KVM: TDX: Report CORE_CAPABILITIES as configurable
2026-09-17 7:25 [PATCH v4 0/4] KVM: TDX: Validate directly configurable CPUID bits Binbin Wu
2026-09-17 7:25 ` [PATCH v4 1/4] KVM: TDX: Track configurable CPUID bits allowed by KVM Binbin Wu
@ 2026-09-17 7:25 ` Binbin Wu
2026-09-17 7:25 ` [PATCH v4 3/4] KVM: TDX: Filter configurable CPUID bits Binbin Wu
2026-09-17 7:25 ` [PATCH v4 4/4] KVM: TDX: Validate userspace CPUID input for KVM_TDX_INIT_VM Binbin Wu
3 siblings, 0 replies; 5+ messages in thread
From: Binbin Wu @ 2026-09-17 7:25 UTC (permalink / raw)
To: linux-kernel, kvm
Cc: seanjc, pbonzini, dave.hansen, andrew.cooper3, nik.borisov, kas,
rick.p.edgecombe, xiaoyao.li, chao.gao, tony.lindgren,
kishen.maloor, dedekind1, binbin.wu
Add CORE_CAPABILITIES (CPUID.0x7.0.EDX[30]) to KVM's allowlist of TDX
directly configurable CPUID feature bits, even though KVM doesn't support
MSR_IA32_CORE_CAPS for TDX guests, to accommodate the legacy TDX module
definition and userspace's stale knowledge of it.
Older TDX specifications define the CORE_CAPABILITIES CPUID bit as
fixed-1, so userspace may expect the bit to be enabled for TDs. #VE
reduction turns it into a directly configurable bit, so leaving it out of
the allowlist would make the bit impossible to enable once KVM starts
validating userspace's CPUID input, i.e. would be a surprising behavior
change for such userspace.
Reporting CORE_CAPABILITIES as directly configurable also lets userspace
detect that the bit is no longer fixed-1, and thus correct its stale
knowledge.
Keep MSR_IA32_CORE_CAPS unsupported for TDs, as no existing TDX user needs
guest access to the MSR.
Note, CORE_CAPABILITIES is the only bit that is unsupported by KVM *and*
changed from fixed-1 to directly configurable by #VE reduction, and no
further #VE reductions are expected.
Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
Reviewed-by: Tony Lindgren <tony.lindgren@linux.intel.com>
---
v4:
- Add #VE reduction related background to the changelog. (Kishen)
- Add RB from Tony.
v3:
- Drop the code for MSR_IA32_CORE_CAPS access.
---
arch/x86/kvm/vmx/tdx.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c
index 2b51a85c998e8..b34afc52b714e 100644
--- a/arch/x86/kvm/vmx/tdx.c
+++ b/arch/x86/kvm/vmx/tdx.c
@@ -165,6 +165,13 @@ static void __init tdx_initialize_cpu_cfg_caps(void)
TDX_CFG_F(AVX512_VP2INTERSECT),
TDX_CFG_F(SERIALIZE),
TDX_CFG_F(TSXLDTRK),
+ /*
+ * KVM doesn't support MSR_IA32_CORE_CAPS, but older TDX specs
+ * define this bit as fixed-1. Report it as configurable to
+ * accommodate the legacy TDX module definition, and to let
+ * userspace detect that the bit is no longer fixed-1.
+ */
+ TDX_CFG_EXTRA_F(CORE_CAPABILITIES),
);
tdx_cpu_cfg_cap_init(CPUID_7_1_EAX,
--
2.46.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 3/4] KVM: TDX: Filter configurable CPUID bits
2026-09-17 7:25 [PATCH v4 0/4] KVM: TDX: Validate directly configurable CPUID bits Binbin Wu
2026-09-17 7:25 ` [PATCH v4 1/4] KVM: TDX: Track configurable CPUID bits allowed by KVM Binbin Wu
2026-09-17 7:25 ` [PATCH v4 2/4] KVM: TDX: Report CORE_CAPABILITIES as configurable Binbin Wu
@ 2026-09-17 7:25 ` Binbin Wu
2026-09-17 7:25 ` [PATCH v4 4/4] KVM: TDX: Validate userspace CPUID input for KVM_TDX_INIT_VM Binbin Wu
3 siblings, 0 replies; 5+ messages in thread
From: Binbin Wu @ 2026-09-17 7:25 UTC (permalink / raw)
To: linux-kernel, kvm
Cc: seanjc, pbonzini, dave.hansen, andrew.cooper3, nik.borisov, kas,
rick.p.edgecombe, xiaoyao.li, chao.gao, tony.lindgren,
kishen.maloor, dedekind1, binbin.wu
Filter the directly configurable CPUID bits reported through
KVM_TDX_CAPABILITIES against KVM's TDX allowlist, and drop the hardcoded
denylist based filtering.
The TDX module reports directly configurable CPUID bits that it supports
for a TD, but KVM must not expose bits that it doesn't support, as blindly
exposing a host state clobbering feature can lead to host state corruption.
The existing denylist, which clears only TSX and WAITPKG, is not fail-safe.
Add tdx_get_cpuid_cfg_mask() to get the mask of directly configurable bits
allowed by KVM for a given CPUID register, covering both feature bits,
which come from tdx_cpu_cfg_caps[], and non-feature bits, which are
enumerated at runtime. Apply the mask to every CPUID entry reported
through KVM_TDX_CAPABILITIES.
With the allowlist in place, newly introduced TDX directly configurable
CPUID bits stay hidden from userspace until KVM explicitly opts in.
Note, filtering KVM_TDX_CAPABILITIES intentionally stops advertising the
directly configurable bits that aren't in the allowlist, as the
corresponding features are unsupported or cannot be properly virtualized.
Update the documentation to reflect the ABI change.
Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
---
v4:
- Rename functions. (Tony)
tdx_cfg_non_feature_mask() -> tdx_get_cpuid_cfg_non_feature_mask()
tdx_cfg_feature_mask() -> tdx_get_cpuid_cfg_feature_mask()
tdx_get_allowed_cfg_cpuid_mask() -> tdx_get_cpuid_cfg_mask()
- Update documentation. (Xiaoyao, Rick)
v3:
- Handle non-feature leafs at runtime. (Sean)
- Add CPUID.0x24.0.EBX[7:0] into allowlist. There is a mismatch of the
description about CPUID.0x24.0.EBX[7:0], which is listed as
"XFAM & CPUID_Enabled & Native" but should be "XFAM & CPUID_Enabled &
Configured & Native".
---
Documentation/virt/kvm/x86/intel-tdx.rst | 8 ++
arch/x86/kvm/vmx/tdx.c | 95 ++++++++++++++++++------
2 files changed, 80 insertions(+), 23 deletions(-)
diff --git a/Documentation/virt/kvm/x86/intel-tdx.rst b/Documentation/virt/kvm/x86/intel-tdx.rst
index 6a222e9d09541..6beeb89d7f057 100644
--- a/Documentation/virt/kvm/x86/intel-tdx.rst
+++ b/Documentation/virt/kvm/x86/intel-tdx.rst
@@ -69,6 +69,14 @@ Return the TDX capabilities that current KVM supports with the specific TDX
module loaded in the system. It reports what features/capabilities are allowed
to be configured to the TDX guest.
+Note, a CPUID feature bit that the TDX module reports as directly configurable
+is not necessarily reported as configurable by KVM. KVM omits features it
+doesn't support. Generally speaking, KVM reports a feature as configurable
+only if KVM supports the feature for both TDX and non-TDX VMs, though there are
+a handful of exceptions where KVM allows a feature for TDX guests that it never
+advertises for non-TDX VMs. Userspace must rely on KVM_TDX_CAPABILITIES to
+determine what can be passed in cpuid to KVM_TDX_INIT_VM.
+
- id: KVM_TDX_CAPABILITIES
- flags: must be 0
- data: pointer to struct kvm_tdx_capabilities
diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c
index b34afc52b714e..ad7d70b36ffe5 100644
--- a/arch/x86/kvm/vmx/tdx.c
+++ b/arch/x86/kvm/vmx/tdx.c
@@ -294,36 +294,79 @@ static bool has_tsx(const struct kvm_cpuid_entry2 *entry)
(entry->ebx & TDX_FEATURE_TSX);
}
-static void clear_tsx(struct kvm_cpuid_entry2 *entry)
-{
- entry->ebx &= ~TDX_FEATURE_TSX;
-}
-
static bool has_waitpkg(const struct kvm_cpuid_entry2 *entry)
{
return entry->function == 7 && entry->index == 0 &&
(entry->ecx & __feature_bit(X86_FEATURE_WAITPKG));
}
-static void clear_waitpkg(struct kvm_cpuid_entry2 *entry)
-{
- entry->ecx &= ~__feature_bit(X86_FEATURE_WAITPKG);
-}
-
-static void tdx_clear_unsupported_cpuid(struct kvm_cpuid_entry2 *entry)
-{
- if (has_tsx(entry))
- clear_tsx(entry);
-
- if (has_waitpkg(entry))
- clear_waitpkg(entry);
-}
-
static bool tdx_unsupported_cpuid(const struct kvm_cpuid_entry2 *entry)
{
return has_tsx(entry) || has_waitpkg(entry);
}
+#define TDX_CPUID_ALL_ALLOWED_MASK GENMASK_U32(31, 0)
+
+static u32 tdx_get_cpuid_cfg_non_feature_mask(u32 function, u32 index, int reg)
+{
+ /*
+ * For a leaf/subleaf/register that will never be repurposed to hold
+ * feature bits, it's safe to return TDX_CPUID_ALL_ALLOWED_MASK, i.e.
+ * leave the TDX module's CPUID config mask intact.
+ */
+ switch (function) {
+ case 1:
+ if (reg == CPUID_EAX || reg == CPUID_EBX)
+ return TDX_CPUID_ALL_ALLOWED_MASK;
+ return 0;
+ case 4:
+ case 0x18:
+ case 0x1f:
+ return TDX_CPUID_ALL_ALLOWED_MASK;
+ case 0x24:
+ if (index == 0 && reg == CPUID_EBX)
+ return GENMASK_U32(7, 0);
+ return 0;
+ case 0x80000008:
+ if (reg == CPUID_EAX)
+ return TDX_CPUID_ALL_ALLOWED_MASK;
+ return 0;
+ default:
+ return 0;
+ }
+}
+
+static u32 tdx_get_cpuid_cfg_feature_mask(u32 function, u32 index, int reg)
+{
+ for (int i = 0; i < NR_KVM_CPU_CAPS; i++) {
+ const struct cpuid_reg *cpuid = &reverse_cpuid[i];
+
+ if (!cpuid->function)
+ continue;
+
+ if (cpuid->function == function && cpuid->index == index &&
+ cpuid->reg == reg)
+ return tdx_cpu_cfg_caps[i];
+ }
+
+ return 0;
+}
+
+static u32 tdx_get_cpuid_cfg_mask(u32 function, u32 index, int reg)
+{
+ u32 non_feature_mask = tdx_get_cpuid_cfg_non_feature_mask(function, index, reg);
+
+ /* Skip reverse_cpuid[] walk if it's already all allowed. */
+ if (non_feature_mask == TDX_CPUID_ALL_ALLOWED_MASK)
+ return TDX_CPUID_ALL_ALLOWED_MASK;
+
+ /*
+ * It's possible that a CPUID register contains both feature and
+ * non-feature bits.
+ */
+ return non_feature_mask | tdx_get_cpuid_cfg_feature_mask(function, index, reg);
+}
+
#define KVM_TDX_CPUID_NO_SUBLEAF ((__u32)-1)
static void td_init_cpuid_entry2(struct kvm_cpuid_entry2 *entry, unsigned char idx)
@@ -347,8 +390,6 @@ static void td_init_cpuid_entry2(struct kvm_cpuid_entry2 *entry, unsigned char i
*/
if (entry->function == 0x80000008)
entry->eax = tdx_set_guest_phys_addr_bits(entry->eax, 0xff);
-
- tdx_clear_unsupported_cpuid(entry);
}
#define TDVMCALLINFO_SETUP_EVENT_NOTIFY_INTERRUPT BIT(1)
@@ -371,8 +412,16 @@ static int init_kvm_tdx_caps(const struct tdx_sys_info_td_conf *td_conf,
caps->user_tdvmcallinfo_1_r11 =
TDVMCALLINFO_SETUP_EVENT_NOTIFY_INTERRUPT;
- for (i = 0; i < td_conf->num_cpuid_config; i++)
- td_init_cpuid_entry2(&caps->cpuid.entries[i], i);
+ for (i = 0; i < td_conf->num_cpuid_config; i++) {
+ struct kvm_cpuid_entry2 *e = &caps->cpuid.entries[i];
+
+ td_init_cpuid_entry2(e, i);
+ /* Only report the configurable bits allowed by KVM. */
+ e->eax &= tdx_get_cpuid_cfg_mask(e->function, e->index, CPUID_EAX);
+ e->ebx &= tdx_get_cpuid_cfg_mask(e->function, e->index, CPUID_EBX);
+ e->ecx &= tdx_get_cpuid_cfg_mask(e->function, e->index, CPUID_ECX);
+ e->edx &= tdx_get_cpuid_cfg_mask(e->function, e->index, CPUID_EDX);
+ }
return 0;
}
--
2.46.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v4 4/4] KVM: TDX: Validate userspace CPUID input for KVM_TDX_INIT_VM
2026-09-17 7:25 [PATCH v4 0/4] KVM: TDX: Validate directly configurable CPUID bits Binbin Wu
` (2 preceding siblings ...)
2026-09-17 7:25 ` [PATCH v4 3/4] KVM: TDX: Filter configurable CPUID bits Binbin Wu
@ 2026-09-17 7:25 ` Binbin Wu
3 siblings, 0 replies; 5+ messages in thread
From: Binbin Wu @ 2026-09-17 7:25 UTC (permalink / raw)
To: linux-kernel, kvm
Cc: seanjc, pbonzini, dave.hansen, andrew.cooper3, nik.borisov, kas,
rick.p.edgecombe, xiaoyao.li, chao.gao, tony.lindgren,
kishen.maloor, dedekind1, binbin.wu
Validate the CPUID configuration provided by userspace through
KVM_TDX_INIT_VM against KVM's TDX allowlist, and drop the hardcoded
denylist based check.
The TDX module lets the VMM configure certain CPUID features for a TD at
initialization time, but KVM must strictly govern which of them userspace
can actually enable, otherwise a host state clobbering feature could be
enabled behind KVM's back. The existing check only rejects TSX and
WAITPKG, i.e. it is not fail-safe, as any bit that a future TDX module
makes configurable would be accepted even if KVM has no idea about the
feature.
Add tdx_has_unsupported_cpuid_cfg_bit() and reject KVM_TDX_INIT_VM if
userspace sets any bit outside the mask returned by
tdx_get_cpuid_cfg_mask(). There is no need to first mask the userspace
input with the bits the TDX module reports as directly configurable, as
anything outside that set is rejected by the TDX module itself.
Also reject CPUID entries whose index differs from the value expected by
the TDX module, as kvm_find_cpuid_entry2() ignores the index when
KVM_CPUID_FLAG_SIGNIFCANT_INDEX is cleared, i.e. a mismatching entry could
otherwise be applied to the wrong subleaf.
Update the comments for KVM_TDX_INIT_VM in the uapi header and the TDX
documentation accordingly.
Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
Reviewed-by: Tony Lindgren <tony.lindgren@linux.intel.com>
---
v4:
- Update the comments/documentation.
- Collect RB tag from Tony.
v3:
- Check CPUID entry index mismatch b/t userspace input and TDX sysinfo
configuration. (Sashiko)
- No need to mask the userspace input with TDX module reported directly
configurable bits first, since the userspace input should be subset of
directly configurable bits. Otherwise, the input will be rejected by
the TDX module.
---
Documentation/virt/kvm/x86/intel-tdx.rst | 2 ++
arch/x86/include/uapi/asm/kvm.h | 2 ++
arch/x86/kvm/vmx/tdx.c | 41 ++++++++++++------------
3 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/Documentation/virt/kvm/x86/intel-tdx.rst b/Documentation/virt/kvm/x86/intel-tdx.rst
index 6beeb89d7f057..36bd0fee2480d 100644
--- a/Documentation/virt/kvm/x86/intel-tdx.rst
+++ b/Documentation/virt/kvm/x86/intel-tdx.rst
@@ -135,6 +135,8 @@ KVM_CREATE_VM and before creating any VCPUs.
/*
* Call KVM_TDX_INIT_VM before vcpu creation, thus before
* KVM_SET_CPUID2.
+ * KVM validates @cpuid, i.e. setting a bit that KVM_TDX_CAPABILITIES
+ * doesn't report as configurable fails the ioctl.
* This configuration supersedes KVM_SET_CPUID2s for VCPUs because the
* TDX module directly virtualizes those CPUIDs without VMM. The user
* space VMM, e.g. qemu, should make KVM_SET_CPUID2 consistent with
diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h
index 1585ec8040666..784cb5cd7f664 100644
--- a/arch/x86/include/uapi/asm/kvm.h
+++ b/arch/x86/include/uapi/asm/kvm.h
@@ -1032,6 +1032,8 @@ struct kvm_tdx_init_vm {
/*
* Call KVM_TDX_INIT_VM before vcpu creation, thus before
* KVM_SET_CPUID2.
+ * KVM validates @cpuid, i.e. setting a bit that KVM_TDX_CAPABILITIES
+ * doesn't report as configurable fails the ioctl.
* This configuration supersedes KVM_SET_CPUID2s for VCPUs because the
* TDX module directly virtualizes those CPUIDs without VMM. The user
* space VMM, e.g. qemu, should make KVM_SET_CPUID2 consistent with
diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c
index ad7d70b36ffe5..5426191905d0d 100644
--- a/arch/x86/kvm/vmx/tdx.c
+++ b/arch/x86/kvm/vmx/tdx.c
@@ -286,25 +286,6 @@ static u32 tdx_set_guest_phys_addr_bits(const u32 eax, int addr_bits)
return (eax & ~GENMASK(23, 16)) | (addr_bits & 0xff) << 16;
}
-#define TDX_FEATURE_TSX (__feature_bit(X86_FEATURE_HLE) | __feature_bit(X86_FEATURE_RTM))
-
-static bool has_tsx(const struct kvm_cpuid_entry2 *entry)
-{
- return entry->function == 7 && entry->index == 0 &&
- (entry->ebx & TDX_FEATURE_TSX);
-}
-
-static bool has_waitpkg(const struct kvm_cpuid_entry2 *entry)
-{
- return entry->function == 7 && entry->index == 0 &&
- (entry->ecx & __feature_bit(X86_FEATURE_WAITPKG));
-}
-
-static bool tdx_unsupported_cpuid(const struct kvm_cpuid_entry2 *entry)
-{
- return has_tsx(entry) || has_waitpkg(entry);
-}
-
#define TDX_CPUID_ALL_ALLOWED_MASK GENMASK_U32(31, 0)
static u32 tdx_get_cpuid_cfg_non_feature_mask(u32 function, u32 index, int reg)
@@ -2548,6 +2529,17 @@ static int setup_tdparams_eptp_controls(struct kvm_cpuid2 *cpuid,
return 0;
}
+static bool tdx_has_unsupported_cpuid_cfg_bit(const struct kvm_cpuid_entry2 *entry)
+{
+ u32 function = entry->function;
+ u32 index = entry->index;
+
+ return (entry->eax & ~tdx_get_cpuid_cfg_mask(function, index, CPUID_EAX)) ||
+ (entry->ebx & ~tdx_get_cpuid_cfg_mask(function, index, CPUID_EBX)) ||
+ (entry->ecx & ~tdx_get_cpuid_cfg_mask(function, index, CPUID_ECX)) ||
+ (entry->edx & ~tdx_get_cpuid_cfg_mask(function, index, CPUID_EDX));
+}
+
static int setup_tdparams_cpuids(struct kvm_cpuid2 *cpuid,
struct td_params *td_params)
{
@@ -2571,7 +2563,16 @@ static int setup_tdparams_cpuids(struct kvm_cpuid2 *cpuid,
if (!entry)
continue;
- if (tdx_unsupported_cpuid(entry))
+ /*
+ * Reject entries whose index doesn't match the expected one.
+ * This catches userspace passing a CPUID entry with the
+ * KVM_CPUID_FLAG_SIGNIFCANT_INDEX flag cleared when the index
+ * is significant.
+ */
+ if (entry->index != tmp.index)
+ return -EINVAL;
+
+ if (tdx_has_unsupported_cpuid_cfg_bit(entry))
return -EINVAL;
copy_cnt++;
--
2.46.0
^ permalink raw reply [flat|nested] 5+ messages in thread