[PATCH v3] drm/msm/dp: allow eDP sinks without DP_SINK_COUNT

[PATCH v3] drm/msm/dp: allow eDP sinks without DP_SINK_COUNT

[Vivek Kumar]

Some eDP sinks, especially fixed-format eDP-to-HDMI bridge chips with
no downstream AUX-capable panel behind them, do not report a non-zero
DP_SINK_COUNT even though they participate normally in DPCD capability
exchange and link training.

Treating sink_count == 0 as a permanent disconnect is valid for external
DisplayPort, but it breaks eDP probe/enable paths in
msm_dp_display_prepare_link().

Use the same eDP exemption as drm_dp_read_sink_count_cap() for the raw
sink_count checks in this driver, via a small shared helper, so valid eDP
outputs are not rejected as disconnected just because the downstream sink
does not expose a usable DP_SINK_COUNT.

Tested on a Qualcomm QCS6490-based board driving a fixed-format
eDP-to-HDMI bridge IC (chrontel,ch7218a).

Signed-off-by: Vivek Kumar <vk092kumar@gmail.com>
---
 drivers/gpu/drm/msm/dp/dp_aux.c  |  8 ++++++++
 drivers/gpu/drm/msm/dp/dp_aux.h  |  1 +
 drivers/gpu/drm/msm/dp/dp_link.c | 10 ++++++++++
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c
index 3825a2fb48e2..3b5a4da93122 100644
--- a/drivers/gpu/drm/msm/dp/dp_aux.c
+++ b/drivers/gpu/drm/msm/dp/dp_aux.c
@@ -679,6 +679,14 @@ u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux)
 	return status;
 }
 
+bool msm_dp_aux_is_edp(struct drm_dp_aux *msm_dp_aux)
+{
+	struct msm_dp_aux_private *aux =
+		container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux);
+
+	return aux->is_edp;
+}
+
 struct drm_dp_aux *msm_dp_aux_get(struct device *dev,
 			      struct phy *phy,
 			      bool is_edp,
diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h
index 4be02e8b4d0b..9ab401c8526f 100644
--- a/drivers/gpu/drm/msm/dp/dp_aux.h
+++ b/drivers/gpu/drm/msm/dp/dp_aux.h
@@ -22,6 +22,7 @@ void msm_dp_aux_hpd_intr_enable(struct drm_dp_aux *msm_dp_aux);
 void msm_dp_aux_hpd_intr_disable(struct drm_dp_aux *msm_dp_aux);
 u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux *msm_dp_aux);
 u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux);
+bool msm_dp_aux_is_edp(struct drm_dp_aux *msm_dp_aux);
 
 struct phy;
 struct drm_dp_aux *msm_dp_aux_get(struct device *dev,
diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
index 34a91e194a12..bf08b5b18097 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.c
+++ b/drivers/gpu/drm/msm/dp/dp_link.c
@@ -725,6 +725,16 @@ static int msm_dp_link_parse_sink_status_field(struct msm_dp_link_private *link)
 		DRM_ERROR("DP parse sink count failed\n");
 		return ret;
 	}
+
+	/*
+	 * Some eDP sinks do not report a valid sink count, even though they
+	 * otherwise participate in link training and DPCD capability exchange.
+	 * Treat a zero raw count as a valid non-zero placeholder so we do not
+	 * misclassify the link as disconnected on eDP.
+	 */
+	if (msm_dp_aux_is_edp(link->aux) && ret == 0)
+		ret = 1;
+
 	link->msm_dp_link.sink_count = ret;
 
 	ret = drm_dp_dpcd_read_link_status(link->aux,
-- 
2.55.0