[PATCH iwl-net 0/2] ice: DPLL init fixes for E810 timing boards

[PATCH iwl-net 0/2] ice: DPLL init fixes for E810 timing boards

[Petr Oros]

Two fixes for E810-C timing boards the driver's static pin tables were
not written for, seen on a board whose netlist has no PCA9575 clock mux
and whose CGU reports more pins than the tables describe. The first
layout is a reference design of its own, Intel ships it as the
E810_C827_SyncE_SFP_SEC NVM configuration.

Patch 1 keeps the DPLL registration alive when the PCA9575 clock mux is
missing. Today the lookup fails and the driver gives up on the whole
DPLL, so userspace loses both devices and every pin.

Patch 2 stops the SMA and U.FL wrapper setup from indexing the input
and output arrays at fixed positions when the driver has already fallen
back to generic pins, where those positions can lie past the end of the
arrays.

Both are tested on an E810-T with the mux present, with the mux hidden
from the driver, and with the generic pin path forced, and on the board
above, where both DPLLs now lock.

A follow-up for iwl-next derives the generic pin names from the pin
classification the firmware reports, so such boards get addressable
pins instead of ambiguous numbers.

Petr Oros (2):
  ice: fix DPLL registration on boards without the SMA clock mux
  ice: skip the SW pin description on boards with generic DPLL pins

 drivers/net/ethernet/intel/ice/ice_dpll.c | 33 +++++++++++++++++------
 1 file changed, 25 insertions(+), 8 deletions(-)

-- 
2.55.0

[PATCH iwl-net 1/2] ice: fix DPLL registration on boards without the SMA clock mux

[Petr Oros]

The SMA and U.FL connectors of an E810-C timing board are routed by a
PCA9575 GPIO expander, and ice_dpll_init_info_sw_pins() reaches it
through ice_read_sma_ctrl(). On a board that carries a CGU but no such
expander the netlist lookup fails with -ENXIO, which aborts
ice_dpll_init_info() and with it the whole DPLL registration:

  ice 0000:cc:00.0: ice_dpll_init_info - fail: d->inputs:...
  ice 0000:cc:00.0: DPLLs init failure err:-6

Userspace loses the EEC and PPS devices, every CGU pin and the recovered
clock pin.

The netlist describes the mux with a clock mux node, which
ice_init_feature_support() already turns into ICE_F_SMA_CTRL. Key the
software controlled pins on that flag. Without the mux the SMA wrappers
stay inputs, the state the mux path programs at init anyway, and do not
advertise DIRECTION_CAN_CHANGE. The U.FL pins are the other leg of the
mux, so they are hidden, and the outgoing CGU pins stay visible as
REF-SMA1 and REF-SMA2/U.FL2.

The layout is not exotic, the E810_C827_SyncE_SFP_SEC configuration in
Intel's 4.80 NVM package has no clock mux node either. Such boards
worked until the SMA and U.FL redesign moved the expander access into
the DPLL init path.

Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
Cc: stable@vger.kernel.org
Signed-off-by: Petr Oros <poros@redhat.com>
---
 drivers/net/ethernet/intel/ice/ice_dpll.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 85a74cd6ea1f3e..e0362b6bf332e5 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -107,6 +107,9 @@ static const struct dpll_pin_frequency ice_esync_range[] = {
  */
 static bool ice_dpll_is_sw_pin(struct ice_pf *pf, u8 index, bool input)
 {
+	if (!input && !ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
+		return false;
+
 	if (input && pf->hw.device_id == ICE_DEV_ID_E810C_QSFP)
 		index -= ICE_DPLL_SW_PIN_INPUT_BASE_QSFP -
 			 ICE_DPLL_SW_PIN_INPUT_BASE_SFP;
@@ -1213,6 +1216,8 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p,
 
 	if (p->direction == direction && p->active)
 		return 0;
+	if (!ice_is_feature_supported(p->pf, ICE_F_SMA_CTRL))
+		return -EOPNOTSUPP;
 	ret = ice_read_sma_ctrl(&p->pf->hw, &data);
 	if (ret)
 		return ret;
@@ -4510,9 +4515,14 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 						  true, &freq_supp_num);
 		pin->prop.freq_supported_num = freq_supp_num;
 		pin->prop.capabilities =
-			(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE |
-			 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE |
-			 caps);
+			(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | caps);
+		if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
+			pin->prop.capabilities |=
+				DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
+		} else {
+			pin->active = true;
+			pin->direction = DPLL_PIN_DIRECTION_INPUT;
+		}
 		pin->pf = pf;
 		pin->prop.board_label = ice_dpll_sw_pin_sma[i];
 		pin->input = &d->inputs[pin_abs_idx];
@@ -4526,6 +4536,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 		pin->idx = i;
 		pin->prop.type = DPLL_PIN_TYPE_EXT;
 		pin->prop.capabilities = caps;
+		pin->hidden = !ice_is_feature_supported(pf, ICE_F_SMA_CTRL);
 		pin->pf = pf;
 		pin->prop.board_label = ice_dpll_sw_pin_ufl[i];
 		if (i == ICE_DPLL_PIN_SW_1_IDX) {
@@ -4555,6 +4566,9 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 		ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max);
 	}
 
+	if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
+		return 0;
+
 	/* Initialize the SMA control register to a known-good default state.
 	 * Without this write the PCA9575 GPIO expander retains its power-on
 	 * default (all outputs high) which makes all SW pins appear inactive.
-- 
2.55.0

[PATCH iwl-net 2/2] ice: skip the SW pin description on boards with generic DPLL pins

[Petr Oros]

ice_dpll_init_info_sw_pins() describes the SMA and U.FL wrappers by
pointing them at fixed positions of the input and output arrays, inputs
4 and 5 and outputs 0 and 1 on an E810-C SFP, and reads the ref-sync
partner of the input it picked. The arrays are sized by the pin counts
firmware reports. On a board that does not match the Intel reference
layout the driver has already fallen back to generic pins, and when
such a board reports fewer pins than the reference the reads run past
the end of the arrays.

The wrappers are never registered on a generic board, but
ice_dpll_init_pins() still calls ice_dpll_pin_ref_sync_register() on
them, so a stray nonzero partner from the out of bounds read would pair
NULL pins.

Describe the wrappers only when the static pin table is in use and keep
their ref-sync registration under the same condition. The default
programming of the PCA9575 clock mux stays on the generic path, a board
that has the mux still needs its SMA connectors switched to inputs.

Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
Signed-off-by: Petr Oros <poros@redhat.com>
---
 drivers/net/ethernet/intel/ice/ice_dpll.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index e0362b6bf332e5..81bb32d2b23012 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -4124,15 +4124,15 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu)
 			if (ret)
 				goto deinit_sma;
 			count += ICE_DPLL_PIN_SW_NUM;
+			ret = ice_dpll_pin_ref_sync_register(pf->dplls.sma,
+							     ICE_DPLL_PIN_SW_NUM);
+			if (ret)
+				goto deinit_ufl;
 		}
 		ret = ice_dpll_pin_ref_sync_register(pf->dplls.inputs,
 						     pf->dplls.num_inputs);
 		if (ret)
 			goto deinit_ufl;
-		ret = ice_dpll_pin_ref_sync_register(pf->dplls.sma,
-						     ICE_DPLL_PIN_SW_NUM);
-		if (ret)
-			goto deinit_ufl;
 	} else {
 		count += pf->dplls.num_outputs + 2 * ICE_DPLL_PIN_SW_NUM;
 	}
@@ -4501,6 +4501,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 	int i, ret;
 	u8 data;
 
+	if (d->generic)
+		goto init_sma_ctrl;
 	if (pf->hw.device_id == ICE_DEV_ID_E810C_QSFP)
 		input_idx_offset = ICE_E810_RCLK_PINS_NUM;
 	phase_adj_max = max(d->input_phase_adj_max, d->output_phase_adj_max);
@@ -4566,6 +4568,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 		ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max);
 	}
 
+init_sma_ctrl:
 	if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
 		return 0;
 
@@ -4584,7 +4587,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 	if (ret)
 		return ret;
 
-	ret = ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE,
+	ret = ice_dpll_pin_state_update(pf, d->sma, ICE_DPLL_PIN_TYPE_SOFTWARE,
 					NULL);
 	if (ret)
 		return ret;
-- 
2.55.0