[PATCH v2 2/6] iio: adc: ade9000: fix DIPC event never being handled or cleared

[Antoniu Miclaus <antoniu.miclaus@analog.com>]

The STATUS1 interrupt handler scans the enabled interrupt bits using
ADE9000_ST1_CROSSING_DEPTH as both the bitmap size and the exclusive upper
bound of the for_each_set_bit_from() loop. ADE9000_ST1_CROSSING_DEPTH was
25, so the scan only covered bits 6..24 and never examined bit 25,
ADE9000_ST1_DIPC_BIT (phase C voltage dip).

As a result, when userspace enables the DIPC threshold event and it fires,
the handler neither pushes the IIO event nor sets bit 25 in handled_irq.
Since STATUS1 is write-1-to-clear, the DIPC status bit is never cleared and
the interrupt keeps re-asserting, causing an interrupt storm.

Bump ADE9000_ST1_CROSSING_DEPTH to 26 so the scan includes DIPC.

Fixes: 81de7b4619fc ("iio: adc: add ade9000 support")
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
Changes in v2:
- new patch, found by the sashiko review of v1.

 drivers/iio/adc/ade9000.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ade9000.c b/drivers/iio/adc/ade9000.c
index 0f64bfb221da..ce0317766698 100644
--- a/drivers/iio/adc/ade9000.c
+++ b/drivers/iio/adc/ade9000.c
@@ -219,7 +219,7 @@
 #define ADE9000_ST1_ERROR2_BIT		BIT(30)
 #define ADE9000_ST1_ERROR3_BIT		BIT(31)
 #define ADE9000_ST1_CROSSING_FIRST	6
-#define ADE9000_ST1_CROSSING_DEPTH	25
+#define ADE9000_ST1_CROSSING_DEPTH	26
 
 #define ADE9000_WFB_TRG_DIP_BIT		BIT(0)
 #define ADE9000_WFB_TRG_SWELL_BIT	BIT(1)
-- 
2.43.0