[PATCH] drm/amd/display: Fix audio DTO for HDMI YCbCr 4:2:0 on DCE

[PATCH] drm/amd/display: Fix audio DTO for HDMI YCbCr 4:2:0 on DCE

[Igor Paunovic]

On DCE 11.2, 11.22 and 12.x, audio runs at twice the sample rate while
an HDMI sink is in YCbCr 4:2:0. DTO0 is shared, so a DisplayPort
monitor on the same GPU is sped up as well.

get_pixel_clock_parameters() halves requested_pix_clk_100hz for 4:2:0.
The PHY PLL is programmed from that rate, but
dce112_program_pixel_clk_resync() sets PIXCLK_DOUBLE_RATE_ENABLE, so the
CRTC that feeds DTO0 keeps the full rate. build_audio_output() still
passes the halved rate on as the DTO0 module, which gives 48 MHz
instead of 24 MHz; its 4:2:0 branch is skipped on DCE, because the
requested clock is halved already.

Program the DTO0 module with twice requested_pix_clk_100hz when the HDMI
stream's clock source doubles the pixel clock, tested through the mask
field that enables the doubling; only the DCE 11.2, 11.22 and 12.x
clock sources have it. ACR (N/CTS) and az_configure() use a separately
built audio_output and do not change.

Lu Yao's patch (Link) doubles both clocks, but only for POLARIS12, which
also moves ACR to the 594 MHz table entry.

Tested on an RX 580 (Polaris10) with a TV at 3840x2160@60 4:2:0 and a
monitor on DP: DP audio was audibly sped up before the patch; after it,
a 17.63 s clip played in 17.71 s on DP and 17.70 s on HDMI.
DCCG_AUDIO_DTO0_MODULE now reads 5940000, the CRTC frame counter gives
60.00 Hz on a 4400x2250 raster (594 MHz), HDMI ACR status reads N=5120,
CTS=247500, and DP audio M readback (996) is the same as with the TV at
3840x2160@30.

Fixes: 87b58768eccd ("drm/amd/display: audio bug fix part 1: Add missing audio ACR")
Link: https://lore.kernel.org/all/20251205074344.143063-1-yaolu@kylinos.cn/
Assisted-by: LLM sparse checkpatch
Signed-off-by: Igor Paunovic <royalnet026@gmail.com>
---

Not tested: the other DCE 11.2/11.22/12.x parts (Polaris11/12, VEGAM,
Vega), and 4:2:0 with deep color, which this sink cannot take (300 MHz
TMDS limit). DCN is left alone on purpose: its OTG halves the horizontal
timing for 4:2:0 (optc1_is_two_pixels_per_container()), so the halved
module is right there.

The host is an arm64 board (RK3588) and the RX 580 sits in an M.2
slot as an external GPU (PCIe 8.0 GT/s x4), not an x86 desktop.
The kernel under test was 7.3-rc3 plus local patches, one of which
touches the same 4:2:0 path (a longer REG_WAIT in dce_opp.c, not
submitted). The patch as posted was built and checked with sparse on
drm-amdgpu-next and on amd-staging-drm-next (arm64, W=1 C=1, no new
warnings for this file), but no module built from those trees was
loaded on the card.

An LLM assistant helped me trace the clock path, do the arithmetic and
write the patch and this message; sparse and checkpatch were run on the
result. The numbers above are wall-clock times and register reads taken
on the board.

Possibly the same bug, although none of the reports mentions 4:2:0:
https://gitlab.freedesktop.org/drm/amd/-/issues/3088 (RX 590, 60 Hz
double speed, 30 Hz fine), and the closed #556, #1742 and #922.
 .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index bb46d72490259..45c64c473a8cc 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -51,6 +51,7 @@
 #include "link_service.h"
 #include "dccg.h"
 #include "clock_source.h"
+#include "dce/dce_clock_source.h"
 #include "clk_mgr.h"
 #include "abm.h"
 #include "audio.h"
@@ -2519,6 +2520,38 @@ static void dce110_reset_hw_ctx_wrap(
 	}
 }
 
+/*
+ * Audio wall clock DTO0 is fed by the CRTC pixel clock, so its module must be
+ * the rate the CRTC really runs at.
+ *
+ * For HDMI YCbCr 4:2:0, get_pixel_clock_parameters() halves
+ * requested_pix_clk_100hz, the PHY PLL is programmed at that rate and
+ * dce112_program_pixel_clk_resync() sets PIXCLK_DOUBLE_RATE_ENABLE, so the
+ * CRTC runs at twice requested_pix_clk_100hz. Only the DCE 11.2/12.x clock
+ * sources have that field in their mask.
+ *
+ * The audio_output used for ACR (N/CTS) is built separately and keeps the
+ * TMDS rate.
+ */
+static void dce110_audio_dto_fixup_420(const struct pipe_ctx *pipe_ctx,
+				       struct audio_crtc_info *crtc_info)
+{
+	const struct dce110_clk_src *clk_src;
+
+	if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A ||
+	    !pipe_ctx->stream_res.pix_clk_params.flags.SUPPORT_YCBCR420 ||
+	    !pipe_ctx->clock_source ||
+	    pipe_ctx->clock_source->id == CLOCK_SOURCE_ID_DP_DTO)
+		return;
+
+	clk_src = TO_DCE110_CLK_SRC(pipe_ctx->clock_source);
+	if (!clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
+		return;
+
+	crtc_info->calculated_pixel_clock_100Hz =
+		pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz * 2;
+}
+
 static void dce110_setup_audio_dto(
 		struct dc *dc,
 		struct dc_state *context)
@@ -2559,6 +2592,7 @@ static void dce110_setup_audio_dto(
 			struct audio_output audio_output;
 
 			build_audio_output(context, pipe_ctx, &audio_output);
+			dce110_audio_dto_fixup_420(pipe_ctx, &audio_output.crtc_info);
 
 			if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
 				struct dtbclk_dto_params dto_params = {0};

base-commit: e0e9c2257911b291ef5345635a9e6dfef5b2b424
-- 
2.43.0