Re: [PATCH v12 0/15] ax88179_178a: Add support for AX88179A-based chips

[Jianhui Xu <neuromoments@gmail.com>]

Hi Birger,

I tested v12 on the same ASIX AX88179B adapter. All 15 patches applied to
the declared base 1bb784eb6e38fd73143f021608e4ef3095d0c0d7. The full
kernel/modules build and focused W=1 builds for phylink.o, phy.o,
ax88179.o, and ax88796b.o passed.

For QEMU runtime testing I again applied Chen-Yu Tsai's `usb: xhci: Fix
HCS_ERST_MAX conversion` patch. Without it, this base cannot initialize
QEMU's xHCI controller. No AX88179 or PHY source was changed.

The fresh functional run completed cold DHCP at 1000baseT/Full without
a reload and passed the 1000/100/10/1000 Mbit/s matrix, EEE
disable/restore, pause enable/restore, EEPROM read, module reload, and QEMU
USB detach/reattach. Ten additional 100/full-to-1000/full cycles passed
both endpoints with bound traffic and RX growth; I did not reproduce the
earlier carrier-loss or carrier-without-RX failures.

I also directly exercised the new phylink MII ioctl path. Read-only
SIOCGMIIPHY and SIOCGMIIREG requests both succeeded and returned PHY
address 3 and register 0 value 0x1040.

One fresh `wol d` and three independent fresh `wol g` QEMU deep-S3 cycles
all passed. Every cycle was monitor-confirmed suspended, resumed at
1000baseT/Full, and passed immediate, +10-second, and +20-second traffic/RX
checks.

Tested-by: Jianhui Xu <neuromoments@gmail.com>

Thanks,
Jianhui