From: Slark Xiao <slark_xiao@163.com>
To: mani@kernel.org, jeff.hugo@oss.qualcomm.com
Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, Slark Xiao <slark_xiao@163.com>
Subject: [PATCH] bus: mhi: host: pci_generic: Add autosuspend_delay customized support
Date: Sat, 19 Sep 2026 17:55:06 +0800 [thread overview]
Message-ID: <20260919095506.9570-1-slark_xiao@163.com> (raw)
For some WWAN device, it may get a SYS ERROR issue when resuming
from suspend state frequently. Refer to the Qualcomm Windows
driver, the default value of autosuspend_delay_ms is set as 5000
ms. But in Linux side, all WWAN device were set as 2000ms. We
tried to set this value to 5000ms and we can get a positive test
result.
So we add a support to allow vendor to set a difference value for
specific WWAN device.
BTW, based on the principle of structure alignment, I moved the
location of 'trigger_edl'.
Signed-off-by: Slark Xiao <slark_xiao@163.com>
---
drivers/bus/mhi/host/pci_generic.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
index b636e2c23b4d..3339b9b2d16d 100644
--- a/drivers/bus/mhi/host/pci_generic.c
+++ b/drivers/bus/mhi/host/pci_generic.c
@@ -23,6 +23,8 @@
#define HEALTH_CHECK_PERIOD (HZ * 2)
+#define AUTOSUSPEND_DELAY_MS 2000
+
/* PCI VID definitions */
#define PCI_VENDOR_ID_THALES 0x1269
#define PCI_VENDOR_ID_QUECTEL 0x1eac
@@ -38,11 +40,12 @@
* @name: name of the PCI module
* @fw: firmware path (if any)
* @edl: emergency download mode firmware path (if any)
- * @edl_trigger: capable of triggering EDL mode in the device (if supported)
* @bar_num: PCI base address register to use for MHI MMIO register space
* @dma_data_width: DMA transfer word size (32 or 64 bits)
* @vf_dma_data_width: DMA transfer word size for VF's (optional)
* @mru_default: default MRU size for MBIM network packets
+ * @autosuspend_delay: customized autosuspend_delay_ms value for specific mhi device
+ * @edl_trigger: capable of triggering EDL mode in the device (if supported)
* @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
* of inband wake support (such as sdx24)
* @no_m3: M3 not supported
@@ -54,11 +57,12 @@ struct mhi_pci_dev_info {
const char *name;
const char *fw;
const char *edl;
- bool edl_trigger;
unsigned int bar_num;
unsigned int dma_data_width;
unsigned int vf_dma_data_width;
unsigned int mru_default;
+ unsigned int autosuspend_delay;
+ bool edl_trigger;
bool sideband_wake;
bool no_m3;
bool reset_on_remove;
@@ -1369,6 +1373,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
struct mhi_pci_device *mhi_pdev;
struct mhi_controller *mhi_cntrl;
unsigned int dma_data_width;
+ unsigned int autosuspend_delay;
int err;
dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name);
@@ -1394,6 +1399,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
dma_data_width = (pdev->is_virtfn && info->vf_dma_data_width) ?
info->vf_dma_data_width : info->dma_data_width;
+ autosuspend_delay = info->autosuspend_delay ? info->autosuspend_delay :
+ AUTOSUSPEND_DELAY_MS;
+
mhi_cntrl->cntrl_dev = &pdev->dev;
mhi_cntrl->iova_start = 0;
mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(dma_data_width);
@@ -1463,7 +1471,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
/* Allow runtime suspend only if both PME from D3Hot and M3 are supported */
if (pci_pme_capable(pdev, PCI_D3hot) && !(info->no_m3)) {
- pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
+ pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
--
2.25.1
next reply other threads:[~2026-09-19 9:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-19 9:55 Slark Xiao [this message]
2026-09-22 4:12 ` Krishna Chaitanya Chundru
2026-09-22 11:39 ` Slark Xiao
2026-09-23 3:54 ` Krishna Chaitanya Chundru
2026-09-23 9:49 ` Slark Xiao
2026-09-26 11:26 ` Manivannan Sadhasivam
2026-10-08 8:40 ` Slark Xiao
2026-10-11 9:46 ` Manivannan Sadhasivam
2026-10-15 6:13 ` Slark Xiao
2026-10-15 13:51 ` Manivannan Sadhasivam
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