[PATCH DNI v2 00/11] media: rcar-fcp, vsp1: Enable on R-Car X5H

[PATCH DNI v2 00/11] media: rcar-fcp, vsp1: Enable on R-Car X5H

[Paul Elder]

This series is based on Geert's
"topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3" branch [0]. A
branch including this series is available here [1].

This series enables the FCPV{B,I,D} and the VSP{B,I,D} blocks on the Renesas
R-Car X5H SoC.

This has been tested on an Ironhide with the vsp-tests test suite [2].
VSPI:
145 tests: 138 passed, 0 failed, 7 skipped
VSPB:
115 tests: 104 passed, 0 failed, 11 skipped
VSPD (a):
114 tests: 99 passed, 0 failed, 15 skipped

VSPD (b) hangs on the tests, so that needs some investigation.

The first couple patches add clocks that are used by the FCP and VSP,
but as the upstream X5H CPG driver is barebones at the moment and we
don't yet ensure that the parents are enabled, these are marked as DNI
for the moment.

The last patch checks the device revision and prints it, which is useful
for debugging but is unnecessary processing for driver operation so it
is marked as DNI as well.

There was some odd behavior with the clocks, where from what I
understood was that the clocks for the FCPV{B,I} and VSP{B,I} are
always-on, but the tests would hang unless I explicitly enabled...  the
always-on clock (or fsleep). Then after I removed the patch that
explicitly enabled the always-on clock everything ran fine. Just
reporting that this happened just in case it's relevant.

[0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3
[1] https://git.ideasonboard.com/epaul/linux/src/branch/epaul/v7.3-rc1/x5h/vsp/fcp
[2] https://git.ideasonboard.com/renesas/vsp-tests/commit/900168f58c9d96be0592c2593f4d8f34edc9c69e

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
Changes in v2:
- Add FCPVD and VSPD
- Fixed author (I mistakenly overwrote a few when I renamed my email)
- Link to v1: https://lore.kernel.org/r/20260917-epaul-v7-3-rc1-x5h-vsp-fcp-v1-0-4c72d4e086dd@ideasonboard.com

---
Laurent Pinchart (4):
      arm64: renesas: r8a78000: Add VSP[BI] nodes
      media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3
      media: vsp1: Document X5H SoC ID
      [DNI] media: rcar-fcp: Check device revision at probe time

Paul Elder (7):
      [DNI] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}
      [DNI] clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36
      pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36
      arm64: renesas: r8a78000: Add FCPV[BI] nodes
      arm64: renesas: r8a78000: Add FCPVD and VSPD nodes
      media: vsp1: Add device info entries for VSPD on X5H
      media: rcar-fcp: Handle resets

 arch/arm64/boot/dts/renesas/r8a78000.dtsi        | 361 +++++++++++++++++++++++
 drivers/clk/renesas/r8a78000-cpg.c               |   2 +
 drivers/media/platform/renesas/rcar-fcp.c        | 158 +++++++++-
 drivers/media/platform/renesas/vsp1/vsp1_drv.c   |  35 ++-
 drivers/media/platform/renesas/vsp1/vsp1_regs.h  |   4 +-
 drivers/pmdomain/renesas/r8a78000-mdlc.c         |  54 +++-
 include/dt-bindings/clock/renesas,r8a78000-cpg.h |   2 +
 7 files changed, 601 insertions(+), 15 deletions(-)
---
base-commit: 02c5d61866607bce0b3271e7c1b838c53dbedc55
change-id: 20260917-epaul-v7-3-rc1-x5h-vsp-fcp-8afdeb2740f7

Best regards,
-- 
Paul Elder <paul.elder+renesas@ideasonboard.com>

[PATCH DNI v2 01/11] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}

[Paul Elder]

Add the CPG_SGD4_VIO_DP_TX and CPG_SGD4_VIO_DP_OTHER clocks. The former
is used by FCPV{B,D,I} and VSPD while the latter is used by VSP{B,I} on
the Renesas R-Car X5H.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 include/dt-bindings/clock/renesas,r8a78000-cpg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
index 5851a29847f961b9b4ec270f263eb3aa19e45308..8c1a01e28ddbb26c583d7c9b387400ef6626c06c 100644
--- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -12,5 +12,7 @@
 #define R8A78000_CPG_SGASYNCD16_PERW_BUS	2
 #define R8A78000_CPG_S0D4_PERE_MAIN		3	// FIXME Preliminary
 #define R8A78000_CPG_MSOCK_PERW_BUS		4	// FIXME Preliminary
+#define R8A78000_CPG_SGD4_VIO_DP_TX		5	// FIXME Preliminary
+#define R8A78000_CPG_SGD4_VIO_DP_OTHER		6	// FIXME Preliminary
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */

-- 
2.47.3

[PATCH DNI v2 02/11] clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36

[Paul Elder]

Add clocks for the FCPV{B,D,I} and VSP{B,D, I}. They each have one clock
from an option of two: a 1066MHz and a quarter-divided 266MHz. As we
already have support for the 266MHz one, add just those for now.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/clk/renesas/r8a78000-cpg.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
index b820d09e1a195068debe8a6eea7a01c534a97b23..17792ff6ab8ae2f7eb5c8f7e3d581b43177e195d 100644
--- a/drivers/clk/renesas/r8a78000-cpg.c
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -326,6 +326,8 @@ static const struct clk_map_in r8a78000_cpg_fw_4_31_0[] = {
 	{ R8A78000_CPG_SGASYNCD16_PERW_BUS,	FIXED_CLK(66M) },
 	{ R8A78000_CPG_S0D4_PERE_MAIN,		FIXED_CLK(200M) },
 	{ R8A78000_CPG_MSOCK_PERW_BUS,		1667 },
+	{ R8A78000_CPG_SGD4_VIO_DP_TX,		FIXED_CLK(266M)},
+	{ R8A78000_CPG_SGD4_VIO_DP_OTHER,	FIXED_CLK(266M)},
 	{ -1 }
 };
 

-- 
2.47.3

[PATCH v2 03/11] pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36

[Paul Elder]

Add maps for VIO for the VSP and FCP power domains and reset domains.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

---
Changes in v2:
- add VSPD and FCPVD
---
 drivers/pmdomain/renesas/r8a78000-mdlc.c | 54 ++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
index a0d83f27735e7deacb060e4102e510726b34e62e..cabe6435ecd791e358fd6987ce9394898d8c87f8 100644
--- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
+++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
@@ -861,6 +861,56 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_28_0[] = {
 	{ /* sentinel */ }
 };
 
+static const struct power_map_in r8a78000_mdlc_vio_power_fw_4_31_0[] = {
+	{ 0, 4 },	/* PD_VIO0 */
+	{ 1, 5 },	/* PD_VIO1 */
+	{ 2, 6 },	/* PD_VIO2 */
+	{ 3, 7 },	/* PD_VIO3 */
+	{ 7, 11 },	/* PD_VIO4 */
+	{ -1 }
+};
+static const struct mod_map_in r8a78000_mdlc_vio_mod_fw_4_31_0[] = {
+	{ 0x70, 26 },	/* VSPD0 */
+	{ 0x71, 27 },	/* VSPD1 */
+	{ 0x72, 28 },	/* VSPD2 */
+	{ 0x73, 29 },	/* VSPD3 */
+	{ 0x74, 30 },	/* VSPD4 */
+	{ 0x75, 31 },	/* VSPDB0 */
+	{ 0x76, 32 },	/* VSPDB1 */
+	{ 0x77, 33 },	/* VSPDB2 */
+	{ 0x78, 34 },	/* VSPDB3 */
+	{ 0x79, 35 },	/* VSPDB4 */
+	{ 0x7e, 40 },	/* FCPVD0 */
+	{ 0x7f, 41 },	/* FCPVD1 */
+	{ 0x80, 42 },	/* FCPVD2 */
+	{ 0x81, 43 },	/* FCPVD3 */
+	{ 0x82, 44 },	/* FCPVD4 */
+	{ 0x83, 45 },	/* FCPVD5 */
+	{ 0x84, 46 },	/* FCPVD6 */
+	{ 0x85, 47 },	/* FCPVD7 */
+	{ 0x86, 48 },	/* FCPVD8 */
+	{ 0x87, 49 },	/* FCPVD9 */
+	{ 0xf9, 163 },	/* VSPB0 */
+	{ 0xfa, 164 },	/* VSPB1 */
+	{ 0xfb, 165 },	/* VSPB2 */
+	{ 0xfc, 166 },	/* VSPB3 */
+	{ 0xfd, 167 },	/* VSPB4 */
+	{ 0xfe, 168 },	/* VSPI0 */
+	{ 0xff, 169 },	/* VSPI1 */
+	{ 0x100, 170 },	/* VSPI2 */
+	{ 0x101, 171 },	/* VSPI3 */
+	{ 0x102, 172 },	/* FCPVB0 */
+	{ 0x103, 173 },	/* FCPVB1 */
+	{ 0x104, 174 },	/* FCPVB2 */
+	{ 0x105, 175 },	/* FCPVB3 */
+	{ 0x106, 176 },	/* FCPVB4 */
+	{ 0x107, 177 },	/* FCPVI0 */
+	{ 0x108, 178 },	/* FCPVI1 */
+	{ 0x109, 179 },	/* FCPVI2 */
+	{ 0x10a, 180 },	/* FCPVI3 */
+	{ -1 }
+};
+
 static const struct mod_map_in r8a78000_mdlc_pere_mod_fw_4_31_0[] = {
 	{ 0x30, 193 },	/* PERE_GPIODM0 */
 	// No CLOCK_ATTRIBUTES { 0x31, 194 },	/* PERE_GPIODM1 */
@@ -997,8 +1047,8 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_31_0[] = {
 		/* FIXME .mod_map = r8a78000_mdlc_vips_mod_fw_4_31_0, */
 	}, {
 		.base = 0xc5000000 /* mdlc_vio */,
-		/* FIXME .power_map = r8a78000_mdlc_vio_power_fw_4_28_0, */
-		/* FIXME .mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0, */
+		.power_map = r8a78000_mdlc_vio_power_fw_4_31_0,
+		.mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0,
 	}, {
 		.base = 0xc08f0000 /* mdlc_pere */,
 		.power_map = r8a78000_mdlc_pere_power_fw_4_28_0,

-- 
2.47.3

[PATCH v2 04/11] arm64: renesas: r8a78000: Add FCPV[BI] nodes

[Paul Elder]

Add DT nodes for the FCPVB and FCPVI IP cores in the R-Car X5H SoC.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 72 +++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 9a07753b221541ed49a975e0c95f2f5d1fdc6ac2..2f8886f8b6545026397fd83969882f8c62afa9d3 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1000,6 +1000,78 @@ mdlc_aon: system-controller@c1338000 {
 			bootph-all;
 		};
 
+		fcpvi0: fcp@c5030000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5030000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x107>;
+			resets = <&mdlc_vio 0x107>;
+		};
+
+		fcpvi1: fcp@c5031000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5031000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x108>;
+			resets = <&mdlc_vio 0x108>;
+		};
+
+		fcpvi2: fcp@c5032000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5032000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x109>;
+			resets = <&mdlc_vio 0x109>;
+		};
+
+		fcpvi3: fcp@c5033000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5033000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x10a>;
+			resets = <&mdlc_vio 0x10a>;
+		};
+
+		fcpvb0: fcp@c5038000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5038000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x102>;
+			resets = <&mdlc_vio 0x102>;
+		};
+
+		fcpvb1: fcp@c5039000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5039000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x103>;
+			resets = <&mdlc_vio 0x103>;
+		};
+
+		fcpvb2: fcp@c503a000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503a000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x104>;
+			resets = <&mdlc_vio 0x104>;
+		};
+
+		fcpvb3: fcp@c503b000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503b000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x105>;
+			resets = <&mdlc_vio 0x105>;
+		};
+
+		fcpvb4: fcp@c503c000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503c000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x106>;
+			resets = <&mdlc_vio 0x106>;
+		};
+
 		mdlc_cmnn: system-controller@ca410000 {
 			compatible = "renesas,r8a78000-mdlc";
 			reg = <0 0xca410000 0 0x1000>;

-- 
2.47.3

[PATCH v2 05/11] arm64: renesas: r8a78000: Add VSP[BI] nodes

[Paul Elder]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Add DT nodes for the VSPB and VSPI IP cores in the R-Car X5H SoC.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 99 +++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 2f8886f8b6545026397fd83969882f8c62afa9d3..f90b869579d384e3fc13d0a13625b7cddaac2868 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1072,6 +1072,105 @@ fcpvb4: fcp@c503c000 {
 			resets = <&mdlc_vio 0x106>;
 		};
 
+		vspi0: vsp@c5080000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5080000 0 0x8000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfe>;
+			resets = <&mdlc_vio 0xfe>;
+
+			renesas,fcp = <&fcpvi0>;
+		};
+
+		vspi1: vsp@c5088000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5088000 0 0x8000>;
+			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xff>;
+			resets = <&mdlc_vio 0xff>;
+
+			renesas,fcp = <&fcpvi1>;
+		};
+
+		vspi2: vsp@c5090000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5090000 0 0x8000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0x100>;
+			resets = <&mdlc_vio 0x100>;
+
+			renesas,fcp = <&fcpvi2>;
+		};
+
+		vspi3: vsp@c5098000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5098000 0 0x8000>;
+			interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0x101>;
+			resets = <&mdlc_vio 0x101>;
+
+			renesas,fcp = <&fcpvi3>;
+		};
+
+		vspb0: vsp@c50c0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50c0000 0 0x8000>;
+			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xf9>;
+			resets = <&mdlc_vio 0xf9>;
+
+			renesas,fcp = <&fcpvb0>;
+		};
+
+		vspb1: vsp@c50c8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50c8000 0 0x8000>;
+			interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfa>;
+			resets = <&mdlc_vio 0xfa>;
+
+			renesas,fcp = <&fcpvb1>;
+		};
+
+		vspb2: vsp@c50d0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50d0000 0 0x8000>;
+			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfb>;
+			resets = <&mdlc_vio 0xfb>;
+
+			renesas,fcp = <&fcpvb2>;
+		};
+
+		vspb3: vsp@c50d8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50d8000 0 0x8000>;
+			interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfc>;
+			resets = <&mdlc_vio 0xfc>;
+
+			renesas,fcp = <&fcpvb3>;
+		};
+
+		vspb4: vsp@c50e0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50e0000 0 0x8000>;
+			interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfd>;
+			resets = <&mdlc_vio 0xfd>;
+
+			renesas,fcp = <&fcpvb4>;
+		};
+
 		mdlc_cmnn: system-controller@ca410000 {
 			compatible = "renesas,r8a78000-mdlc";
 			reg = <0 0xca410000 0 0x1000>;

-- 
2.47.3

[PATCH v2 06/11] arm64: renesas: r8a78000: Add FCPVD and VSPD nodes

[Paul Elder]

Add DT nodes for the FCPVD and VSPD IP cores in the R-Car X5H SoC.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 190 ++++++++++++++++++++++++++++++
 1 file changed, 190 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index f90b869579d384e3fc13d0a13625b7cddaac2868..21b83531a5b6ceec02dd11f6bccdd40d253bb42d 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1000,6 +1000,196 @@ mdlc_aon: system-controller@c1338000 {
 			bootph-all;
 		};
 
+		fcpvd0: fcp@c5010000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5010000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x7e>;
+			resets = <&mdlc_vio 0x7e>;
+		};
+
+		fcpvd1: fcp@c5011000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5011000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x7f>;
+			resets = <&mdlc_vio 0x7f>;
+		};
+
+		fcpvd2: fcp@c5012000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5012000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x80>;
+			resets = <&mdlc_vio 0x80>;
+		};
+
+		fcpvd3: fcp@c5013000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5013000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x81>;
+			resets = <&mdlc_vio 0x81>;
+		};
+
+		fcpvd4: fcp@c5014000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5014000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x82>;
+			resets = <&mdlc_vio 0x82>;
+		};
+
+		fcpvd5: fcp@c5015000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5015000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x83>;
+			resets = <&mdlc_vio 0x83>;
+		};
+
+		fcpvd6: fcp@c5016000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5016000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x84>;
+			resets = <&mdlc_vio 0x84>;
+		};
+
+		fcpvd7: fcp@c5017000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5017000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x85>;
+			resets = <&mdlc_vio 0x85>;
+		};
+
+		fcpvd8: fcp@c5018000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5018000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x86>;
+			resets = <&mdlc_vio 0x86>;
+		};
+
+		fcpvd9: fcp@c5019000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5019000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x87>;
+			resets = <&mdlc_vio 0x87>;
+		};
+
+		vspd0: vsp@c4800000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4800000 0 0x8000>;
+			interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x70>;
+			resets = <&mdlc_vio 0x70>;
+
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		vspd1: vsp@c4808000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4808000 0 0x8000>;
+			interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x71>;
+			resets = <&mdlc_vio 0x71>;
+
+			renesas,fcp = <&fcpvd1>;
+		};
+
+		vspd2: vsp@c4810000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4810000 0 0x8000>;
+			interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x72>;
+			resets = <&mdlc_vio 0x72>;
+
+			renesas,fcp = <&fcpvd2>;
+		};
+
+		vspd3: vsp@c4818000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4818000 0 0x8000>;
+			interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x73>;
+			resets = <&mdlc_vio 0x73>;
+
+			renesas,fcp = <&fcpvd3>;
+		};
+
+		vspd4: vsp@c4820000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4820000 0 0x8000>;
+			interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x74>;
+			resets = <&mdlc_vio 0x74>;
+
+			renesas,fcp = <&fcpvd4>;
+		};
+
+		vspdb0: vsp@c4828000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4828000 0 0x8000>;
+			interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x75>;
+			resets = <&mdlc_vio 0x75>;
+
+			renesas,fcp = <&fcpvd5>;
+		};
+
+		vspdb1: vsp@c4830000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4830000 0 0x8000>;
+			interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x76>;
+			resets = <&mdlc_vio 0x76>;
+
+			renesas,fcp = <&fcpvd6>;
+		};
+
+		vspdb2: vsp@c4838000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4838000 0 0x8000>;
+			interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x77>;
+			resets = <&mdlc_vio 0x77>;
+
+			renesas,fcp = <&fcpvd7>;
+		};
+
+		vspdb3: vsp@c4840000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4840000 0 0x8000>;
+			interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x78>;
+			resets = <&mdlc_vio 0x78>;
+
+			renesas,fcp = <&fcpvd8>;
+		};
+
+		vspdb4: vsp@c4848000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc4848000 0 0x8000>;
+			interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x79>;
+			resets = <&mdlc_vio 0x79>;
+
+			renesas,fcp = <&fcpvd9>;
+		};
+
 		fcpvi0: fcp@c5030000 {
 			compatible = "renesas,fcpv";
 			reg = <0 0xc5030000 0 0x1000>;

-- 
2.47.3

[PATCH v2 07/11] media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3

[Paul Elder]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The M3-W, M3-N and E3 SoCs integrate a VSPB that reports the same
version ID as the VSPBD in the H3 and H3-N, but includes additional
entities compared to the VSPBD. The VSPBD device entry in the driver
matches on the version ID only, which results in the VSPB being handled
as a VSPBD. The driver therefore doesn't support the CLU, LUT and HGO
entities in the M3-W, M3-N and E3 SoCs.

To fix it, split the device entry in two, one for the VSPBD with an
additional SoC ID match, and one for the VSPB. The VSPBD entry needs to
be listed first, otherwise the VSPB entry will match on H3 and H3-N as
well.

The VI6_IP_VERSION_MODEL_VSPBD_GEN3 macro is renamed to
VI6_IP_VERSION_MODEL_VSPB_GEN3 to indicate that the VSPBD is the special
case.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_drv.c  | 13 ++++++++++++-
 drivers/media/platform/renesas/vsp1/vsp1_regs.h |  2 +-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
index 762a9e776a94d50accad070068f92f6dabb81035..5597595414fe787413c7daa5a3142faa9ced8408 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
@@ -781,14 +781,25 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
 		.wpf_count = 1,
 		.uapi = true,
 	}, {
-		.version = VI6_IP_VERSION_MODEL_VSPBD_GEN3,
+		.version = VI6_IP_VERSION_MODEL_VSPB_GEN3,
 		.model = "VSP2-BD",
+		.soc = VI6_IP_VERSION_SOC_H3,
 		.gen = 3,
 		.features = VSP1_HAS_BRU | VSP1_HAS_WPF_VFLIP,
 		.rpf_count = 5,
 		.wpf_count = 1,
 		.num_bru_inputs = 5,
 		.uapi = true,
+	}, {
+		.version = VI6_IP_VERSION_MODEL_VSPB_GEN3,
+		.model = "VSP2-B",
+		.gen = 3,
+		.features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO
+			  | VSP1_HAS_LUT | VSP1_HAS_WPF_VFLIP,
+		.rpf_count = 5,
+		.wpf_count = 1,
+		.num_bru_inputs = 5,
+		.uapi = true,
 	}, {
 		.version = VI6_IP_VERSION_MODEL_VSPBC_GEN3,
 		.model = "VSP2-BC",
diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 10cfbcd1b6e0b3a9c0a8daaa990babfaeb8dde0c..4c0315656e9f81a9656b58fb6f0233f8a22ac0e1 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -792,7 +792,7 @@
 #define VI6_IP_VERSION_MODEL_VSPS_V2H	(0x12 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_V2H	(0x13 << 8)
 #define VI6_IP_VERSION_MODEL_VSPI_GEN3	(0x14 << 8)
-#define VI6_IP_VERSION_MODEL_VSPBD_GEN3	(0x15 << 8)
+#define VI6_IP_VERSION_MODEL_VSPB_GEN3	(0x15 << 8)
 #define VI6_IP_VERSION_MODEL_VSPBC_GEN3	(0x16 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_GEN3	(0x17 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_V3	(0x18 << 8)

-- 
2.47.3

[PATCH v2 08/11] media: vsp1: Document X5H SoC ID

[Paul Elder]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The R-Car X5H uses 0x09 as the SoC ID in the version register. Document
is with a macro, as done for other R-Car SoCs.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

---
Changes in v2:
- Fix the version register number: s/0x04/0x09/
---
 drivers/media/platform/renesas/vsp1/vsp1_regs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 4c0315656e9f81a9656b58fb6f0233f8a22ac0e1..8abf39bac6c2f333696ebf55de87586d2df3bed0 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -816,6 +816,7 @@
 #define VI6_IP_VERSION_SOC_E3		(0x04 << 0)
 #define VI6_IP_VERSION_SOC_V3U		(0x05 << 0)
 #define VI6_IP_VERSION_SOC_V4H		(0x06 << 0)
+#define VI6_IP_VERSION_SOC_X5H		(0x09 << 0)
 /* RZ/G2L SoCs have no version register, So use 0x80 for SoC Identification */
 #define VI6_IP_VERSION_SOC_RZG2L	(0x80 << 0)
 

-- 
2.47.3

[PATCH v2 09/11] media: vsp1: Add device info entries for VSPD on X5H

[Paul Elder]

Add device info entries for the VSPD so that the driver can match on the
VSPD on the X5H and handle it slightly different hardware configuration.

On the X5H there are two variants, the VSPD (a) and VSPD (b). As the (b)
version has a separate version number, add that as well.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_drv.c  | 22 ++++++++++++++++++++++
 drivers/media/platform/renesas/vsp1/vsp1_regs.h |  1 +
 2 files changed, 23 insertions(+)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
index 5597595414fe787413c7daa5a3142faa9ced8408..627771e3056617daa8e10d1fb68218435cde0a64 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
@@ -860,6 +860,17 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
 		.uif_count = 2,
 		.wpf_count = 2,
 		.num_bru_inputs = 5,
+	}, {
+		.version = VI6_IP_VERSION_MODEL_VSPD_GEN4,
+		.model = "VSP2-D (a)",
+		.soc = VI6_IP_VERSION_SOC_X5H,
+		.gen = 4,
+		.features = VSP1_HAS_BRU | VSP1_HAS_EXT_DL,
+		.lif_count = 1,
+		.rpf_count = 5,
+		.uif_count = 2,
+		.wpf_count = 1,
+		.num_bru_inputs = 5,
 	}, {
 		.version = VI6_IP_VERSION_MODEL_VSPD_GEN4,
 		.model = "VSP2-D",
@@ -870,6 +881,17 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
 		.uif_count = 2,
 		.wpf_count = 1,
 		.num_bru_inputs = 5,
+	}, {
+		.version = VI6_IP_VERSION_MODEL_VSPDB_GEN4,
+		.model = "VSP2-D (b)",
+		.soc = VI6_IP_VERSION_SOC_X5H,
+		.gen = 4,
+		.features = VSP1_HAS_BRU | VSP1_HAS_EXT_DL,
+		.lif_count = 1,
+		.rpf_count = 5,
+		.uif_count = 1,
+		.wpf_count = 1,
+		.num_bru_inputs = 5,
 	}, {
 		.version = VI6_IP_VERSION_MODEL_VSPX_GEN4,
 		.model = "VSP2-X",
diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 8abf39bac6c2f333696ebf55de87586d2df3bed0..489d88107d1c17530a74736c40563a93cc17e567 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -800,6 +800,7 @@
 #define VI6_IP_VERSION_MODEL_VSPBS_GEN3	(0x1a << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_GEN4	(0x1c << 8)
 #define VI6_IP_VERSION_MODEL_VSPX_GEN4	(0x1d << 8)
+#define VI6_IP_VERSION_MODEL_VSPDB_GEN4	(0x20 << 8)
 /* RZ/G2L SoCs have no version register, So use 0x80 as the model version */
 #define VI6_IP_VERSION_MODEL_VSPD_RZG2L	(0x80 << 8)
 

-- 
2.47.3

[PATCH v2 10/11] media: rcar-fcp: Handle resets

[Paul Elder]

On some versions of the FCP, such as the one on the X5H, reset control
is required to operate the FCP. Add support for handling resets
optionally, to continue supporting versions that do not require it.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

---
Changes in v2:
- handle errors
---
 drivers/media/platform/renesas/rcar-fcp.c | 30 ++++++++++++++++++++++++++++--
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
index dfb0ca93e854dd0bb8aedfb757fd786ef6e45542..76d4c250b30815d9eac58f9b54ad923748df79f6 100644
--- a/drivers/media/platform/renesas/rcar-fcp.c
+++ b/drivers/media/platform/renesas/rcar-fcp.c
@@ -16,6 +16,7 @@
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 
 #include <media/rcar-fcp.h>
@@ -29,6 +30,7 @@ struct rcar_fcp_device {
 	struct list_head list;
 	struct device *dev;
 	void __iomem *base;
+	struct reset_control *rstc;
 };
 
 static LIST_HEAD(fcp_devices);
@@ -162,20 +164,25 @@ static int rcar_fcp_probe(struct platform_device *pdev)
 
 	fcp->dev = &pdev->dev;
 
+	platform_set_drvdata(pdev, fcp);
+
 	fcp->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(fcp->base))
 		return PTR_ERR(fcp->base);
 
 	dma_set_max_seg_size(fcp->dev, UINT_MAX);
 
+	fcp->rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
+	if (IS_ERR(fcp->rstc))
+		return dev_err_probe(&pdev->dev, PTR_ERR(fcp->rstc),
+				     "failed to get reset control\n");
+
 	pm_runtime_enable(&pdev->dev);
 
 	mutex_lock(&fcp_lock);
 	list_add_tail(&fcp->list, &fcp_devices);
 	mutex_unlock(&fcp_lock);
 
-	platform_set_drvdata(pdev, fcp);
-
 	return 0;
 }
 
@@ -190,6 +197,24 @@ static void rcar_fcp_remove(struct platform_device *pdev)
 	pm_runtime_disable(&pdev->dev);
 }
 
+static int fcp_pm_runtime_suspend(struct device *dev)
+{
+	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
+
+	return reset_control_assert(fcp->rstc);
+}
+
+static int fcp_pm_runtime_resume(struct device *dev)
+{
+	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
+
+	return reset_control_deassert(fcp->rstc);
+}
+
+static const struct dev_pm_ops fcp_pm_ops = {
+	RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
+};
+
 static const struct of_device_id rcar_fcp_of_match[] = {
 	{ .compatible = "renesas,fcpf" },
 	{ .compatible = "renesas,fcpv" },
@@ -202,6 +227,7 @@ static struct platform_driver rcar_fcp_platform_driver = {
 	.remove		= rcar_fcp_remove,
 	.driver		= {
 		.name	= "rcar-fcp",
+		.pm = pm_ptr(&fcp_pm_ops),
 		.of_match_table = rcar_fcp_of_match,
 		.suppress_bind_attrs = true,
 	},

-- 
2.47.3

[PATCH DNI v2 11/11] media: rcar-fcp: Check device revision at probe time

[Paul Elder]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Verify that the device revision register reports a valid value,
otherwise reject the device.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
Changes since v2:

- Add FCP type information
- Reject devices with an unsupported version

Changes since v1:

- Use devm_platform_ioremap_resource()
---
 drivers/media/platform/renesas/rcar-fcp.c | 132 +++++++++++++++++++++++++++---
 1 file changed, 121 insertions(+), 11 deletions(-)

diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
index 76d4c250b30815d9eac58f9b54ad923748df79f6..5f2c483f71f42f0fc614db216c54d65e2372e8fb 100644
--- a/drivers/media/platform/renesas/rcar-fcp.c
+++ b/drivers/media/platform/renesas/rcar-fcp.c
@@ -14,28 +14,78 @@
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/property.h>
 #include <linux/reset.h>
 #include <linux/slab.h>
 
 #include <media/rcar-fcp.h>
 
-#define RCAR_FCP_REG_RST		0x0010
-#define RCAR_FCP_REG_RST_SOFTRST	BIT(0)
-#define RCAR_FCP_REG_STA		0x0018
-#define RCAR_FCP_REG_STA_ACT		BIT(0)
+#define RCAR_FCP_REG_VCR			0x0000
+#define RCAR_FCP_REG_VCR_CATEGORY		(1 << 8)
+#define RCAR_FCP_REG_VCR_REVISION_H3_ES1	(1 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_M3W		(2 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_V3M		(3 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_H3		(4 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_D3		(5 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_M3N		(6 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_V3H		(7 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_E3		(8 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_X5H_V1	(12 << 0)
+
+#define RCAR_FCP_REG_CFG0			0x0004
+#define RCAR_FCP_REG_CFG0_FCPVSEL		BIT(1)
+
+#define RCAR_FCP_REG_RST			0x0010
+#define RCAR_FCP_REG_RST_RIIFRST		BIT(22)
+#define RCAR_FCP_REG_RST_RSIFRST		BIT(21)
+#define RCAR_FCP_REG_RST_DCMPRST		BIT(20)
+#define RCAR_FCP_REG_RST_MODRST			BIT(4)
+#define RCAR_FCP_REG_RST_SOFTRST		BIT(0)
+
+#define RCAR_FCP_REG_STA			0x0018
+#define RCAR_FCP_REG_STA_ACT			BIT(0)
+
+#define RCAR_FCP_REG_TL_CTRL			0x0070
+#define RCAR_FCP_REG_TL_CTRL_TLEN		BIT(31)
+#define RCAR_FCP_REG_TL_CTRL_VPOS_C(n)		((n) << 16)
+#define RCAR_FCP_REG_TL_CTRL_VPOS_Y(n)		((n) << 0)
+
+#define RCAR_FCP_REG_PICINFO1			0x00c4
+#define RCAR_FCP_REG_PICINFO1_STRIDE_DIV16	((n) << 0)
+
+#define RCAR_FCP_REG_BA_ANC_Y0			0x0100
+#define RCAR_FCP_REG_BA_ANC_Y1			0x0104
+#define RCAR_FCP_REG_BA_ANC_Y2			0x0108
+#define RCAR_FCP_REG_BA_ANC_C			0x010c
+#define RCAR_FCP_REG_BA_REF_Y0			0x0110
+#define RCAR_FCP_REG_BA_REF_Y1			0x0114
+#define RCAR_FCP_REG_BA_REF_Y2			0x0118
+#define RCAR_FCP_REG_BA_REF_C			0x011c
+
+enum rcar_fcp_type {
+	RCAR_FCPF,
+	RCAR_FCPV,
+};
 
 struct rcar_fcp_device {
 	struct list_head list;
 	struct device *dev;
 	void __iomem *base;
 	struct reset_control *rstc;
+	enum rcar_fcp_type type;
 };
 
 static LIST_HEAD(fcp_devices);
 static DEFINE_MUTEX(fcp_lock);
 
+static inline u32 rcar_fcp_read(struct rcar_fcp_device *fcp, u32 reg)
+{
+	return ioread32(fcp->base + reg);
+}
+
 static inline void rcar_fcp_write(struct rcar_fcp_device *fcp, u32 reg, u32 val)
 {
 	iowrite32(val, fcp->base + reg);
@@ -154,15 +204,67 @@ EXPORT_SYMBOL_GPL(rcar_fcp_soft_reset);
  * Platform Driver
  */
 
+static int rcar_fcp_setup(struct rcar_fcp_device *fcp)
+{
+	static const char * const models[] = {
+		[RCAR_FCPF] = "FCPF",
+		[RCAR_FCPV] = "FCPV",
+	};
+	static struct {
+		u32 version;
+		const char *name;
+	} versions[] = {
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3_ES1, "H3 ES1.x" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3W, "M3W" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3M, "V3M" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3, "H3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_D3, "D3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3N, "M3N" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3H, "V3H" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_E3, "E3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_X5H_V1, "X5H v1.0" },
+	};
+
+	unsigned int i;
+	u32 version;
+
+	/* Check the device version register. */
+	version = rcar_fcp_read(fcp, RCAR_FCP_REG_VCR);
+
+	for (i = 0; i < ARRAY_SIZE(versions); ++i) {
+		if (versions[i].version == version)
+			break;
+	}
+
+	if (i >= ARRAY_SIZE(versions)) {
+		dev_err(fcp->dev, "Invalid FCP version 0x%08x\n", version);
+		return -ENODEV;
+	}
+
+	dev_dbg(fcp->dev, "%s %s device found\n", models[fcp->type],
+		versions[i].name);
+
+	return 0;
+}
+
+static const struct of_device_id rcar_fcp_of_match[] = {
+	{ .compatible = "renesas,fcpf", .data = (void *)RCAR_FCPF },
+	{ .compatible = "renesas,fcpv", .data = (void *)RCAR_FCPV },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
+
 static int rcar_fcp_probe(struct platform_device *pdev)
 {
 	struct rcar_fcp_device *fcp;
+	int ret;
 
 	fcp = devm_kzalloc(&pdev->dev, sizeof(*fcp), GFP_KERNEL);
 	if (fcp == NULL)
 		return -ENOMEM;
 
 	fcp->dev = &pdev->dev;
+	fcp->type = (enum rcar_fcp_type)device_get_match_data(&pdev->dev);
 
 	platform_set_drvdata(pdev, fcp);
 
@@ -178,12 +280,27 @@ static int rcar_fcp_probe(struct platform_device *pdev)
 				     "failed to get reset control\n");
 
 	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_resume_and_get(&pdev->dev);
+	if (ret < 0)
+		goto error_pm_disable;
+
+	ret = rcar_fcp_setup(fcp);
+	if (ret < 0)
+		goto error_pm_put;
+
+	pm_runtime_put(&pdev->dev);
 
 	mutex_lock(&fcp_lock);
 	list_add_tail(&fcp->list, &fcp_devices);
 	mutex_unlock(&fcp_lock);
 
 	return 0;
+
+error_pm_put:
+	pm_runtime_put(&pdev->dev);
+error_pm_disable:
+	pm_runtime_disable(&pdev->dev);
+	return ret;
 }
 
 static void rcar_fcp_remove(struct platform_device *pdev)
@@ -215,13 +332,6 @@ static const struct dev_pm_ops fcp_pm_ops = {
 	RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
 };
 
-static const struct of_device_id rcar_fcp_of_match[] = {
-	{ .compatible = "renesas,fcpf" },
-	{ .compatible = "renesas,fcpv" },
-	{ },
-};
-MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
-
 static struct platform_driver rcar_fcp_platform_driver = {
 	.probe		= rcar_fcp_probe,
 	.remove		= rcar_fcp_remove,

-- 
2.47.3

Re: [PATCH v2 03/11] pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36

[Laurent Pinchart]

On Sat, Sep 19, 2026 at 02:07:00AM +0900, Paul Elder wrote:
> Add maps for VIO for the VSP and FCP power domains and reset domains.

This also doesn't seem to be a candidate for upstream yet as it depends
on WIP patches for the MDLC driver.

> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> 
> ---
> Changes in v2:
> - add VSPD and FCPVD
> ---
>  drivers/pmdomain/renesas/r8a78000-mdlc.c | 54 ++++++++++++++++++++++++++++++--
>  1 file changed, 52 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> index a0d83f27735e7deacb060e4102e510726b34e62e..cabe6435ecd791e358fd6987ce9394898d8c87f8 100644
> --- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
> +++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> @@ -861,6 +861,56 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_28_0[] = {
>  	{ /* sentinel */ }
>  };
>  
> +static const struct power_map_in r8a78000_mdlc_vio_power_fw_4_31_0[] = {
> +	{ 0, 4 },	/* PD_VIO0 */
> +	{ 1, 5 },	/* PD_VIO1 */
> +	{ 2, 6 },	/* PD_VIO2 */
> +	{ 3, 7 },	/* PD_VIO3 */
> +	{ 7, 11 },	/* PD_VIO4 */
> +	{ -1 }
> +};
> +static const struct mod_map_in r8a78000_mdlc_vio_mod_fw_4_31_0[] = {
> +	{ 0x70, 26 },	/* VSPD0 */
> +	{ 0x71, 27 },	/* VSPD1 */
> +	{ 0x72, 28 },	/* VSPD2 */
> +	{ 0x73, 29 },	/* VSPD3 */
> +	{ 0x74, 30 },	/* VSPD4 */
> +	{ 0x75, 31 },	/* VSPDB0 */
> +	{ 0x76, 32 },	/* VSPDB1 */
> +	{ 0x77, 33 },	/* VSPDB2 */
> +	{ 0x78, 34 },	/* VSPDB3 */
> +	{ 0x79, 35 },	/* VSPDB4 */
> +	{ 0x7e, 40 },	/* FCPVD0 */
> +	{ 0x7f, 41 },	/* FCPVD1 */
> +	{ 0x80, 42 },	/* FCPVD2 */
> +	{ 0x81, 43 },	/* FCPVD3 */
> +	{ 0x82, 44 },	/* FCPVD4 */
> +	{ 0x83, 45 },	/* FCPVD5 */
> +	{ 0x84, 46 },	/* FCPVD6 */
> +	{ 0x85, 47 },	/* FCPVD7 */
> +	{ 0x86, 48 },	/* FCPVD8 */
> +	{ 0x87, 49 },	/* FCPVD9 */
> +	{ 0xf9, 163 },	/* VSPB0 */
> +	{ 0xfa, 164 },	/* VSPB1 */
> +	{ 0xfb, 165 },	/* VSPB2 */
> +	{ 0xfc, 166 },	/* VSPB3 */
> +	{ 0xfd, 167 },	/* VSPB4 */
> +	{ 0xfe, 168 },	/* VSPI0 */
> +	{ 0xff, 169 },	/* VSPI1 */
> +	{ 0x100, 170 },	/* VSPI2 */
> +	{ 0x101, 171 },	/* VSPI3 */
> +	{ 0x102, 172 },	/* FCPVB0 */
> +	{ 0x103, 173 },	/* FCPVB1 */
> +	{ 0x104, 174 },	/* FCPVB2 */
> +	{ 0x105, 175 },	/* FCPVB3 */
> +	{ 0x106, 176 },	/* FCPVB4 */
> +	{ 0x107, 177 },	/* FCPVI0 */
> +	{ 0x108, 178 },	/* FCPVI1 */
> +	{ 0x109, 179 },	/* FCPVI2 */
> +	{ 0x10a, 180 },	/* FCPVI3 */
> +	{ -1 }
> +};
> +
>  static const struct mod_map_in r8a78000_mdlc_pere_mod_fw_4_31_0[] = {
>  	{ 0x30, 193 },	/* PERE_GPIODM0 */
>  	// No CLOCK_ATTRIBUTES { 0x31, 194 },	/* PERE_GPIODM1 */
> @@ -997,8 +1047,8 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_31_0[] = {
>  		/* FIXME .mod_map = r8a78000_mdlc_vips_mod_fw_4_31_0, */
>  	}, {
>  		.base = 0xc5000000 /* mdlc_vio */,
> -		/* FIXME .power_map = r8a78000_mdlc_vio_power_fw_4_28_0, */
> -		/* FIXME .mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0, */
> +		.power_map = r8a78000_mdlc_vio_power_fw_4_31_0,
> +		.mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0,
>  	}, {
>  		.base = 0xc08f0000 /* mdlc_pere */,
>  		.power_map = r8a78000_mdlc_pere_power_fw_4_28_0,
> 

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 06/11] arm64: renesas: r8a78000: Add FCPVD and VSPD nodes

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Sat, Sep 19, 2026 at 02:07:03AM +0900, Paul Elder wrote:
> Add DT nodes for the FCPVD and VSPD IP cores in the R-Car X5H SoC.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> ---
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi | 190 ++++++++++++++++++++++++++++++
>  1 file changed, 190 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index f90b869579d384e3fc13d0a13625b7cddaac2868..21b83531a5b6ceec02dd11f6bccdd40d253bb42d 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1000,6 +1000,196 @@ mdlc_aon: system-controller@c1338000 {
>  			bootph-all;
>  		};
>  
> +		fcpvd0: fcp@c5010000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5010000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x7e>;
> +			resets = <&mdlc_vio 0x7e>;
> +		};
> +
> +		fcpvd1: fcp@c5011000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5011000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x7f>;
> +			resets = <&mdlc_vio 0x7f>;
> +		};
> +
> +		fcpvd2: fcp@c5012000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5012000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x80>;
> +			resets = <&mdlc_vio 0x80>;
> +		};
> +
> +		fcpvd3: fcp@c5013000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5013000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x81>;
> +			resets = <&mdlc_vio 0x81>;
> +		};
> +
> +		fcpvd4: fcp@c5014000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5014000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x82>;
> +			resets = <&mdlc_vio 0x82>;
> +		};
> +
> +		fcpvd5: fcp@c5015000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5015000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x83>;
> +			resets = <&mdlc_vio 0x83>;
> +		};
> +
> +		fcpvd6: fcp@c5016000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5016000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x84>;
> +			resets = <&mdlc_vio 0x84>;
> +		};
> +
> +		fcpvd7: fcp@c5017000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5017000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x85>;
> +			resets = <&mdlc_vio 0x85>;
> +		};
> +
> +		fcpvd8: fcp@c5018000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5018000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x86>;
> +			resets = <&mdlc_vio 0x86>;
> +		};
> +
> +		fcpvd9: fcp@c5019000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5019000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x87>;
> +			resets = <&mdlc_vio 0x87>;
> +		};
> +
> +		vspd0: vsp@c4800000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4800000 0 0x8000>;
> +			interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x70>;
> +			resets = <&mdlc_vio 0x70>;
> +
> +			renesas,fcp = <&fcpvd0>;
> +		};
> +
> +		vspd1: vsp@c4808000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4808000 0 0x8000>;
> +			interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x71>;
> +			resets = <&mdlc_vio 0x71>;
> +
> +			renesas,fcp = <&fcpvd1>;
> +		};
> +
> +		vspd2: vsp@c4810000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4810000 0 0x8000>;
> +			interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x72>;
> +			resets = <&mdlc_vio 0x72>;
> +
> +			renesas,fcp = <&fcpvd2>;
> +		};
> +
> +		vspd3: vsp@c4818000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4818000 0 0x8000>;
> +			interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x73>;
> +			resets = <&mdlc_vio 0x73>;
> +
> +			renesas,fcp = <&fcpvd3>;
> +		};
> +
> +		vspd4: vsp@c4820000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4820000 0 0x8000>;
> +			interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x74>;
> +			resets = <&mdlc_vio 0x74>;
> +
> +			renesas,fcp = <&fcpvd4>;
> +		};
> +
> +		vspdb0: vsp@c4828000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4828000 0 0x8000>;
> +			interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x75>;
> +			resets = <&mdlc_vio 0x75>;
> +
> +			renesas,fcp = <&fcpvd5>;
> +		};
> +
> +		vspdb1: vsp@c4830000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4830000 0 0x8000>;
> +			interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x76>;
> +			resets = <&mdlc_vio 0x76>;
> +
> +			renesas,fcp = <&fcpvd6>;
> +		};
> +
> +		vspdb2: vsp@c4838000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4838000 0 0x8000>;
> +			interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x77>;
> +			resets = <&mdlc_vio 0x77>;
> +
> +			renesas,fcp = <&fcpvd7>;
> +		};
> +
> +		vspdb3: vsp@c4840000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4840000 0 0x8000>;
> +			interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x78>;
> +			resets = <&mdlc_vio 0x78>;
> +
> +			renesas,fcp = <&fcpvd8>;
> +		};
> +
> +		vspdb4: vsp@c4848000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc4848000 0 0x8000>;
> +			interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x79>;
> +			resets = <&mdlc_vio 0x79>;
> +
> +			renesas,fcp = <&fcpvd9>;
> +		};
> +
>  		fcpvi0: fcp@c5030000 {
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xc5030000 0 0x1000>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 08/11] media: vsp1: Document X5H SoC ID

[Laurent Pinchart]

On Sat, Sep 19, 2026 at 02:07:05AM +0900, Paul Elder wrote:
> From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> 
> The R-Car X5H uses 0x09 as the SoC ID in the version register. Document
> is with a macro, as done for other R-Car SoCs.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
> Changes in v2:
> - Fix the version register number: s/0x04/0x09/

Thanks for the fix.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

But I think we can squash this with patch 09/11.

> ---
>  drivers/media/platform/renesas/vsp1/vsp1_regs.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> index 4c0315656e9f81a9656b58fb6f0233f8a22ac0e1..8abf39bac6c2f333696ebf55de87586d2df3bed0 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> @@ -816,6 +816,7 @@
>  #define VI6_IP_VERSION_SOC_E3		(0x04 << 0)
>  #define VI6_IP_VERSION_SOC_V3U		(0x05 << 0)
>  #define VI6_IP_VERSION_SOC_V4H		(0x06 << 0)
> +#define VI6_IP_VERSION_SOC_X5H		(0x09 << 0)
>  /* RZ/G2L SoCs have no version register, So use 0x80 for SoC Identification */
>  #define VI6_IP_VERSION_SOC_RZG2L	(0x80 << 0)
>  

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 09/11] media: vsp1: Add device info entries for VSPD on X5H

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Sat, Sep 19, 2026 at 02:07:06AM +0900, Paul Elder wrote:
> Add device info entries for the VSPD so that the driver can match on the
> VSPD on the X5H and handle it slightly different hardware configuration.

s/it/its/

> 
> On the X5H there are two variants, the VSPD (a) and VSPD (b). As the (b)
> version has a separate version number, add that as well.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  drivers/media/platform/renesas/vsp1/vsp1_drv.c  | 22 ++++++++++++++++++++++
>  drivers/media/platform/renesas/vsp1/vsp1_regs.h |  1 +
>  2 files changed, 23 insertions(+)
> 
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> index 5597595414fe787413c7daa5a3142faa9ced8408..627771e3056617daa8e10d1fb68218435cde0a64 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> @@ -860,6 +860,17 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
>  		.uif_count = 2,
>  		.wpf_count = 2,
>  		.num_bru_inputs = 5,
> +	}, {
> +		.version = VI6_IP_VERSION_MODEL_VSPD_GEN4,
> +		.model = "VSP2-D (a)",
> +		.soc = VI6_IP_VERSION_SOC_X5H,
> +		.gen = 4,
> +		.features = VSP1_HAS_BRU | VSP1_HAS_EXT_DL,
> +		.lif_count = 1,
> +		.rpf_count = 5,
> +		.uif_count = 2,

This is not quite correct, this VSP has 8 UIFs (from UIF0 to UIF7).
However, not only does the driver support at most two UIFs, it hardcodes
usage of one UIF per LIF, and starts at UIF4. Declaring two UIFs here is
fine for the time being, but a comment would be nice.

		/* TODO: The VSP has 8 UIFs, while the driver only support 2. */
		.uif_count = 2,

> +		.wpf_count = 1,
> +		.num_bru_inputs = 5,
>  	}, {
>  		.version = VI6_IP_VERSION_MODEL_VSPD_GEN4,
>  		.model = "VSP2-D",
> @@ -870,6 +881,17 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
>  		.uif_count = 2,
>  		.wpf_count = 1,
>  		.num_bru_inputs = 5,
> +	}, {
> +		.version = VI6_IP_VERSION_MODEL_VSPDB_GEN4,

I think that should be VI6_IP_VERSION_MODEL_VSPDB_GEN5.

> +		.model = "VSP2-D (b)",
> +		.soc = VI6_IP_VERSION_SOC_X5H,

And you can drop the soc match for now, no other SoC uses the version
model ID 0x20.

With those small issues addressed,

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> +		.gen = 4,
> +		.features = VSP1_HAS_BRU | VSP1_HAS_EXT_DL,
> +		.lif_count = 1,
> +		.rpf_count = 5,
> +		.uif_count = 1,
> +		.wpf_count = 1,
> +		.num_bru_inputs = 5,
>  	}, {
>  		.version = VI6_IP_VERSION_MODEL_VSPX_GEN4,
>  		.model = "VSP2-X",
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> index 8abf39bac6c2f333696ebf55de87586d2df3bed0..489d88107d1c17530a74736c40563a93cc17e567 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> @@ -800,6 +800,7 @@
>  #define VI6_IP_VERSION_MODEL_VSPBS_GEN3	(0x1a << 8)
>  #define VI6_IP_VERSION_MODEL_VSPD_GEN4	(0x1c << 8)
>  #define VI6_IP_VERSION_MODEL_VSPX_GEN4	(0x1d << 8)
> +#define VI6_IP_VERSION_MODEL_VSPDB_GEN4	(0x20 << 8)
>  /* RZ/G2L SoCs have no version register, So use 0x80 as the model version */
>  #define VI6_IP_VERSION_MODEL_VSPD_RZG2L	(0x80 << 8)

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 10/11] media: rcar-fcp: Handle resets

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Sat, Sep 19, 2026 at 02:07:07AM +0900, Paul Elder wrote:
> On some versions of the FCP, such as the one on the X5H, reset control
> is required to operate the FCP. Add support for handling resets
> optionally, to continue supporting versions that do not require it.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> ---
> Changes in v2:
> - handle errors
> ---
>  drivers/media/platform/renesas/rcar-fcp.c | 30 ++++++++++++++++++++++++++++--
>  1 file changed, 28 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
> index dfb0ca93e854dd0bb8aedfb757fd786ef6e45542..76d4c250b30815d9eac58f9b54ad923748df79f6 100644
> --- a/drivers/media/platform/renesas/rcar-fcp.c
> +++ b/drivers/media/platform/renesas/rcar-fcp.c
> @@ -16,6 +16,7 @@
>  #include <linux/mutex.h>
>  #include <linux/platform_device.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/reset.h>
>  #include <linux/slab.h>
>  
>  #include <media/rcar-fcp.h>
> @@ -29,6 +30,7 @@ struct rcar_fcp_device {
>  	struct list_head list;
>  	struct device *dev;
>  	void __iomem *base;
> +	struct reset_control *rstc;
>  };
>  
>  static LIST_HEAD(fcp_devices);
> @@ -162,20 +164,25 @@ static int rcar_fcp_probe(struct platform_device *pdev)
>  
>  	fcp->dev = &pdev->dev;
>  
> +	platform_set_drvdata(pdev, fcp);
> +
>  	fcp->base = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(fcp->base))
>  		return PTR_ERR(fcp->base);
>  
>  	dma_set_max_seg_size(fcp->dev, UINT_MAX);
>  
> +	fcp->rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
> +	if (IS_ERR(fcp->rstc))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(fcp->rstc),
> +				     "failed to get reset control\n");
> +
>  	pm_runtime_enable(&pdev->dev);
>  
>  	mutex_lock(&fcp_lock);
>  	list_add_tail(&fcp->list, &fcp_devices);
>  	mutex_unlock(&fcp_lock);
>  
> -	platform_set_drvdata(pdev, fcp);
> -
>  	return 0;
>  }
>  
> @@ -190,6 +197,24 @@ static void rcar_fcp_remove(struct platform_device *pdev)
>  	pm_runtime_disable(&pdev->dev);
>  }
>  
> +static int fcp_pm_runtime_suspend(struct device *dev)
> +{
> +	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
> +
> +	return reset_control_assert(fcp->rstc);
> +}
> +
> +static int fcp_pm_runtime_resume(struct device *dev)
> +{
> +	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
> +
> +	return reset_control_deassert(fcp->rstc);
> +}
> +
> +static const struct dev_pm_ops fcp_pm_ops = {
> +	RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
> +};
> +
>  static const struct of_device_id rcar_fcp_of_match[] = {
>  	{ .compatible = "renesas,fcpf" },
>  	{ .compatible = "renesas,fcpv" },
> @@ -202,6 +227,7 @@ static struct platform_driver rcar_fcp_platform_driver = {
>  	.remove		= rcar_fcp_remove,
>  	.driver		= {
>  		.name	= "rcar-fcp",
> +		.pm = pm_ptr(&fcp_pm_ops),
>  		.of_match_table = rcar_fcp_of_match,
>  		.suppress_bind_attrs = true,
>  	},

-- 
Regards,

Laurent Pinchart