* [PATCH 0/2] ARM: dts: phyCORE-i.MX6 custom OPP table @ 2026-09-23 7:05 Primoz Fiser 2026-09-23 7:05 ` [PATCH 1/2] ARM: dts: imx6dl: Add a label to cpu1 node Primoz Fiser 2026-09-23 7:05 ` [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table Primoz Fiser 0 siblings, 2 replies; 4+ messages in thread From: Primoz Fiser @ 2026-09-23 7:05 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream, Yunus Bas This is a revival of a series originally posted by Yunus Bas in February 2022 [1][2]. It adds a label to the imx6dl cpu1 node and introduces phyCORE-i.MX6 SOM specific operating-points tables, since the phyCORE modules run at slightly different voltage/frequency values than the generic i.MX6Q/DL tables. [1] https://lore.kernel.org/all/20220209223258.1672425-1-y.bas@phytec.de/ [2] https://lore.kernel.org/all/20220209223258.1672425-2-y.bas@phytec.de/ Changes to original series: Patch #1: - update path to nxp/imx Patch #2: - update path to nxp/imx - reformat operating-points/fsl,soc-operating-points as a proper uint32-matrix, addressing Shawn Guo's review original remark. Yunus Bas (2): ARM: dts: imx6dl: Add a label to cpu1 node ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table .../nxp/imx/imx6dl-phytec-mira-rdk-nand.dts | 2 +- .../nxp/imx/imx6dl-phytec-phycore-som.dtsi | 23 ++++++ arch/arm/boot/dts/nxp/imx/imx6dl.dtsi | 2 +- .../nxp/imx/imx6q-phytec-mira-rdk-emmc.dts | 2 +- .../nxp/imx/imx6q-phytec-mira-rdk-nand.dts | 2 +- .../dts/nxp/imx/imx6q-phytec-phycore-som.dtsi | 75 +++++++++++++++++++ 6 files changed, 102 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi -- 2.34.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] ARM: dts: imx6dl: Add a label to cpu1 node 2026-09-23 7:05 [PATCH 0/2] ARM: dts: phyCORE-i.MX6 custom OPP table Primoz Fiser @ 2026-09-23 7:05 ` Primoz Fiser 2026-09-23 7:05 ` [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table Primoz Fiser 1 sibling, 0 replies; 4+ messages in thread From: Primoz Fiser @ 2026-09-23 7:05 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream, Yunus Bas From: Yunus Bas <y.bas@phytec.de> The cpu1 is missing a label for further reference. Since cpu0 has already a label, add also one for cpu1 node, so it can be referenced to add or modify cpu specific properties the same way as cpu0. Signed-off-by: Yunus Bas <y.bas@phytec.de> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> --- arch/arm/boot/dts/nxp/imx/imx6dl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi index dc919e09a505..78092d94f265 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi @@ -48,7 +48,7 @@ cpu0: cpu@0 { nvmem-cell-names = "speed_grade"; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; -- 2.34.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table 2026-09-23 7:05 [PATCH 0/2] ARM: dts: phyCORE-i.MX6 custom OPP table Primoz Fiser 2026-09-23 7:05 ` [PATCH 1/2] ARM: dts: imx6dl: Add a label to cpu1 node Primoz Fiser @ 2026-09-23 7:05 ` Primoz Fiser 1 sibling, 0 replies; 4+ messages in thread From: Primoz Fiser @ 2026-09-23 7:05 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream, Yunus Bas From: Yunus Bas <y.bas@phytec.de> The PHYTEC phyCORE-i.MX6QDL SOM-modules are operating with a slightly different voltage and frequency values in contrast to the generic i.MX6Q/DL tables. The values have been adjusted to achieve the most stable condition for the PHYTEC-modules. Introduce imx6q- and imx6dl-phycore dtsi files with the modified power tables. Signed-off-by: Yunus Bas <y.bas@phytec.de> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> --- .../nxp/imx/imx6dl-phytec-mira-rdk-nand.dts | 2 +- .../nxp/imx/imx6dl-phytec-phycore-som.dtsi | 23 ++++++ .../nxp/imx/imx6q-phytec-mira-rdk-emmc.dts | 2 +- .../nxp/imx/imx6q-phytec-mira-rdk-nand.dts | 2 +- .../dts/nxp/imx/imx6q-phytec-phycore-som.dtsi | 75 +++++++++++++++++++ 5 files changed, 101 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts index d906a7f05aaa..8ec27080ca1e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6dl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi new file mode 100644 index 000000000000..de85c084ac8d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas <y.bas@phytec.de> + */ + +#include "imx6qdl-phytec-phycore-som.dtsi" + +&cpu0 { + operating-points = + /* kHz uV */ + <996000 1275000>, + <792000 1175000>, + <396000 1150000>; +}; + +&cpu1 { + operating-points = + /* kHz uV */ + <996000 1275000>, + <792000 1175000>, + <396000 1150000>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts index 322f071d972f..7d947762f3b9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx6q.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6q-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts index 3f13726c8058..afbb6681a6b5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx6q.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6q-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi new file mode 100644 index 000000000000..ebe05d764357 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas <y.bas@phytec.de> + */ + +#include "imx6qdl-phytec-phycore-som.dtsi" + +&cpu0 { + operating-points = + /* kHz uV */ + <1200000 1300000>, + <996000 1250000>, + <852000 1250000>, + <792000 1175000>, + <396000 1075000>; + fsl,soc-operating-points = + /* ARM kHz SOC-PU uV */ + <1200000 1275000>, + <996000 1250000>, + <852000 1250000>, + <792000 1250000>, + <396000 1250000>; +}; + +&cpu1 { + operating-points = + /* kHz uV */ + <1200000 1300000>, + <996000 1250000>, + <852000 1250000>, + <792000 1175000>, + <396000 1075000>; + fsl,soc-operating-points = + /* ARM kHz SOC-PU uV */ + <1200000 1275000>, + <996000 1250000>, + <852000 1250000>, + <792000 1250000>, + <396000 1250000>; +}; + +&cpu2 { + operating-points = + /* kHz uV */ + <1200000 1300000>, + <996000 1250000>, + <852000 1250000>, + <792000 1175000>, + <396000 1075000>; + fsl,soc-operating-points = + /* ARM kHz SOC-PU uV */ + <1200000 1275000>, + <996000 1250000>, + <852000 1250000>, + <792000 1250000>, + <396000 1250000>; +}; + +&cpu3 { + operating-points = + /* kHz uV */ + <1200000 1300000>, + <996000 1250000>, + <852000 1250000>, + <792000 1175000>, + <396000 1075000>; + fsl,soc-operating-points = + /* ARM kHz SOC-PU uV */ + <1200000 1275000>, + <996000 1250000>, + <852000 1250000>, + <792000 1250000>, + <396000 1250000>; +}; -- 2.34.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] ARM: dts: imx6dl: Add a label to cpu1 node @ 2021-12-13 12:42 Yunus Bas 2021-12-13 12:42 ` [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table Yunus Bas 0 siblings, 1 reply; 4+ messages in thread From: Yunus Bas @ 2021-12-13 12:42 UTC (permalink / raw) To: shawnguo, robh+dt, s.hauer, devicetree Cc: festevam, linux-arm-kernel, linux-kernel The cpu1 is missing a label for further reference. Since cpu0 has already a label, add also one for cpu1 node, so it can be referenced to add or modify cpu specific properties the same way as cpu0. Signed-off-by: Yunus Bas <y.bas@phytec.de> --- arch/arm/boot/dts/imx6dl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index fdd81fdc3f35..d49a9b99f33f 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -48,7 +48,7 @@ cpu0: cpu@0 { nvmem-cell-names = "speed_grade"; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; -- 2.25.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table 2021-12-13 12:42 [PATCH 1/2] ARM: dts: imx6dl: Add a label to cpu1 node Yunus Bas @ 2021-12-13 12:42 ` Yunus Bas 0 siblings, 0 replies; 4+ messages in thread From: Yunus Bas @ 2021-12-13 12:42 UTC (permalink / raw) To: shawnguo, robh+dt, s.hauer, devicetree Cc: festevam, linux-arm-kernel, linux-kernel The PHYTEC phyCORE-i.MX6QDL SOM-modules are operating with a slightly different voltage and frequency values in contrast to the generic i.MX6Q/DL tables. The values have been adjusted to achieve the most stable condition for the PHYTEC-modules. Introduce imx6q- and imx6dl-phycore dtsi files with the modified power tables. Signed-off-by: Yunus Bas <y.bas@phytec.de> --- .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 2 +- .../boot/dts/imx6dl-phytec-phycore-som.dtsi | 25 ++++++ .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 2 +- .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 2 +- .../boot/dts/imx6q-phytec-phycore-som.dtsi | 83 +++++++++++++++++++ 5 files changed, 111 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/imx6dl-phytec-phycore-som.dtsi create mode 100644 arch/arm/boot/dts/imx6q-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index d906a7f05aaa..8ec27080ca1e 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6dl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" diff --git a/arch/arm/boot/dts/imx6dl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6dl-phytec-phycore-som.dtsi new file mode 100644 index 000000000000..0985453b5ad6 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-phytec-phycore-som.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas <y.bas@phytec.de> + */ + +#include "imx6qdl-phytec-phycore-som.dtsi" + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1150000 + >; +}; + +&cpu1 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1150000 + >; +}; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index 322f071d972f..7d947762f3b9 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx6q.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6q-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 3f13726c8058..afbb6681a6b5 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx6q.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6q-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" diff --git a/arch/arm/boot/dts/imx6q-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6q-phytec-phycore-som.dtsi new file mode 100644 index 000000000000..3ecb94379c8b --- /dev/null +++ b/arch/arm/boot/dts/imx6q-phytec-phycore-som.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas <y.bas@phytec.de> + */ + +#include "imx6qdl-phytec-phycore-som.dtsi" + +&cpu0 { + operating-points = < + /* KHz uV */ + 1200000 1300000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1075000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1250000 + 396000 1250000 + >; +}; + +&cpu1 { + operating-points = < + /* KHz uV */ + 1200000 1300000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1075000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1250000 + 396000 1250000 + >; +}; + +&cpu2 { + operating-points = < + /* KHz uV */ + 1200000 1300000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1075000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1250000 + 396000 1250000 + >; +}; + +&cpu3 { + operating-points = < + /* KHz uV */ + 1200000 1300000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1075000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1250000 + 396000 1250000 + >; +}; -- 2.25.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-09-23 7:34 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2026-09-23 7:05 [PATCH 0/2] ARM: dts: phyCORE-i.MX6 custom OPP table Primoz Fiser 2026-09-23 7:05 ` [PATCH 1/2] ARM: dts: imx6dl: Add a label to cpu1 node Primoz Fiser 2026-09-23 7:05 ` [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table Primoz Fiser -- strict thread matches above, loose matches on Subject: below -- 2021-12-13 12:42 [PATCH 1/2] ARM: dts: imx6dl: Add a label to cpu1 node Yunus Bas 2021-12-13 12:42 ` [PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table Yunus Bas
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