* [PATCH v4] drm/msm: default separate_gpu_kms to auto selection
@ 2026-09-28 6:58 Mahadevan P
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From: Mahadevan P @ 2026-09-28 6:58 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Akhil P Oommen,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Mahadevan P
On platforms with multiple display subsystems, such as SA8775P, the GPU
binds to the first display subsystem that probes. This implicit binding
prevents subsequent display subsystems from probing successfully,
breaking multi-display support.
Use the tristate separate_gpu_kms module parameter with the default
value set to auto (-1). In auto mode, the driver selects the binding
behavior based on the number of GPUs and display subsystems. This allows
display subsystems to probe independently when required, while
preserving the existing single-card behavior on simpler systems.
The separate_gpu_kms module parameter has the following semantics:
-1 (auto, default):
Select the binding mode based on hardware topology. If exactly one
GPU and one display subsystem are present, bind them together to
form a single DRM device. Otherwise, expose the GPU and display
subsystems as separate DRM devices.
0:
Always bind the GPU and display together to form a single DRM
device.
1:
Always expose the GPU and display subsystems as separate DRM
devices.
Additionally, ensure that display subsystems are always exposed as
separate DRM devices when no recognized Adreno GPU is present,
regardless of the separate_gpu_kms setting.
This ensures correct probing on multi-display platforms without
affecting single-display, single-GPU systems.
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
---
Changes in v4:
- Fix OF node refcount leak in msm_separate_gpu_kms_components(). (sashiko-bot)
- Fix build errors when MDSS/MDP4 are disabled by adding stubs. (kernel test robot)
- Drop msm_count_mdp5(); MDP5 always sits under a qcom,mdss node, so it was
counted twice.
- adreno_probe(): don't create a standalone GPU device for an unrecognized
GPU.
- Link to v3: https://lore.kernel.org/r/20260330-separate_gpu_kms-v3-1-a3e54b9c9417@oss.qualcomm.com
Changes in v3:
- Ensure display subsystems are always exposed as separate DRM devices when
no recognized Adreno GPU is present (!adreno_has_gpu()), regardless of
separate_gpu_kms setting. (Dmitry)
- Extend auto-selection logic to account for legacy display controllers (MDP4 and MDP5). (Dmitry)
- Rename msm_mdss_count_masters() to msm_mdss_count() to better reflect functionality. (Dmitry)
- Common helper to determine presence of a valid Adreno GPU node, avoiding repeated
adreno_has_gpu() and availability checks.
- Update commit message to reflect the above behavior.
- Link to v2: https://lore.kernel.org/r/20260317-separate_gpu_kms-v2-1-b027ca97b9fe@oss.qualcomm.com
Changes in v2:
- Drop dependency on Lemans dual-DPU device tree changes as this patch
works independently (Dmitry)
- Switch separate_gpu_kms to tristate and default to auto mode (Rob)
- Rename msm_gpu_no_components() to msm_separate_gpu_kms_components() for clarity
- Link to v1: https://lore.kernel.org/r/20260223-seperate_gpu_kms-v1-1-e8231e7f1685@oss.qualcomm.com
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 14 +++++++
drivers/gpu/drm/msm/msm_drv.c | 65 ++++++++++++++++++++++++++----
drivers/gpu/drm/msm/msm_drv.h | 6 ++-
drivers/gpu/drm/msm/msm_mdss.c | 15 +++++++
5 files changed, 95 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 05c77fe27e62..7108d4aa59b5 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -271,8 +271,10 @@ static const struct component_ops a3xx_ops = {
static int adreno_probe(struct platform_device *pdev)
{
- if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") ||
- msm_gpu_no_components())
+ struct device_node *node = pdev->dev.of_node;
+
+ if (of_device_is_compatible(node, "amd,imageon") ||
+ (msm_separate_gpu_kms_components() && adreno_has_gpu(node)))
return msm_gpu_probe(pdev, &a3xx_ops);
return component_add(&pdev->dev, &a3xx_ops);
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 9b1d1982e683..c299fef1a400 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -15,6 +15,20 @@
#include "msm_mmu.h"
#include "mdp4_kms.h"
+static const struct of_device_id mdp4_dt_match[];
+int msm_count_mdp4(void)
+{
+ struct device_node *np;
+ int count = 0;
+
+ for_each_matching_node(np, mdp4_dt_match) {
+ if (of_device_is_available(np))
+ count++;
+ }
+
+ return count;
+}
+
static int mdp4_hw_init(struct msm_kms *kms)
{
struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index f3d2eaa04f14..2ac7fcd468d3 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -54,16 +54,65 @@ static bool modeset = true;
MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
module_param(modeset, bool, 0600);
-static bool separate_gpu_kms;
-MODULE_PARM_DESC(separate_gpu_kms, "Use separate DRM device for the GPU (0=single DRM device for both GPU and display (default), 1=two DRM devices)");
-module_param(separate_gpu_kms, bool, 0400);
+/*
+ * separate_gpu_kms (tristate):
+ * -1 (default): decide automatically based on hardware topology. Split devices
+ * if there is more than one GPU or more than one display master.
+ * 0: force single DRM device (bind display + GPU)
+ * 1: force separate DRM devices
+ */
+static int separate_gpu_kms = -1;
+MODULE_PARM_DESC(separate_gpu_kms,
+ "Use separate DRM device for the GPU (-1=auto (default), 0=single DRM device, 1=separate DRM devices)");
+module_param(separate_gpu_kms, int, 0400);
DECLARE_FAULT_ATTR(fail_gem_alloc);
DECLARE_FAULT_ATTR(fail_gem_iova);
-bool msm_gpu_no_components(void)
+static const struct of_device_id msm_gpu_match[];
+static inline bool msm_gpu_node_present(struct device_node *np)
+{
+ return np && of_device_is_available(np) && adreno_has_gpu(np);
+}
+
+static int msm_count_gpus(void)
{
- return separate_gpu_kms;
+ struct device_node *np;
+ int count = 0;
+
+ for_each_matching_node(np, msm_gpu_match) {
+ if (msm_gpu_node_present(np))
+ count++;
+ }
+
+ return count;
+}
+
+static bool msm_separate_gpu_kms_auto(void)
+{
+ int gpus = msm_count_gpus();
+ int display_subsystems = msm_count_mdss() + msm_count_mdp4();
+
+ if (gpus <= 0 || display_subsystems <= 0)
+ return false;
+
+ /* Single card if there is exactly one GPU and one display subsystem */
+ return gpus > 1 || display_subsystems > 1;
+}
+
+bool msm_separate_gpu_kms_components(void)
+{
+ if (msm_count_gpus() == 0)
+ return true;
+
+ switch (separate_gpu_kms) {
+ case 0:
+ return false;
+ case 1:
+ return true;
+ default:
+ return msm_separate_gpu_kms_auto();
+ }
}
static int msm_drm_uninit(struct device *dev, const struct component_ops *gpu_ops)
@@ -1029,7 +1078,7 @@ static int add_gpu_components(struct device *dev,
if (!np)
return 0;
- if (of_device_is_available(np) && adreno_has_gpu(np))
+ if (msm_gpu_node_present(np))
drm_of_component_match_add(dev, matchptr, component_compare_of, np);
of_node_put(np);
@@ -1040,7 +1089,7 @@ static int add_gpu_components(struct device *dev,
static int msm_drm_bind(struct device *dev)
{
return msm_drm_init(dev,
- msm_gpu_no_components() ?
+ msm_separate_gpu_kms_components() ?
&msm_kms_driver :
&msm_driver,
NULL);
@@ -1079,7 +1128,7 @@ int msm_drv_probe(struct device *master_dev,
return ret;
}
- if (!msm_gpu_no_components()) {
+ if (!msm_separate_gpu_kms_components()) {
ret = add_gpu_components(master_dev, &match);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index eb4bbae8557b..2840e8a5052d 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -394,9 +394,11 @@ static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
#ifdef CONFIG_DRM_MSM_MDP4
void msm_mdp4_register(void);
void msm_mdp4_unregister(void);
+int msm_count_mdp4(void);
#else
static inline void msm_mdp4_register(void) {}
static inline void msm_mdp4_unregister(void) {}
+static inline int msm_count_mdp4(void) { return 0; }
#endif
#ifdef CONFIG_DRM_MSM_MDP5
@@ -418,9 +420,11 @@ static inline void msm_dpu_unregister(void) {}
#ifdef CONFIG_DRM_MSM_MDSS
void msm_mdss_register(void);
void msm_mdss_unregister(void);
+int msm_count_mdss(void);
#else
static inline void msm_mdss_register(void) {}
static inline void msm_mdss_unregister(void) {}
+static inline int msm_count_mdss(void) { return 0; }
#endif
#ifdef CONFIG_DEBUG_FS
@@ -534,6 +538,6 @@ void msm_kms_shutdown(struct platform_device *pdev);
bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver);
-bool msm_gpu_no_components(void);
+bool msm_separate_gpu_kms_components(void);
#endif /* __MSM_DRV_H__ */
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 9087c4b290db..e69b122f2687 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -73,6 +73,21 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
return 0;
}
+static const struct of_device_id mdss_dt_match[];
+
+int msm_count_mdss(void)
+{
+ struct device_node *np;
+ int count = 0;
+
+ for_each_matching_node(np, mdss_dt_match) {
+ if (of_device_is_available(np))
+ count++;
+ }
+
+ return count;
+}
+
static void msm_mdss_irq(struct irq_desc *desc)
{
struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
---
base-commit: 3f2425f5b5bbbdd991ca9cdfd5502e68d8895998
change-id: 20260316-separate_gpu_kms-04d2cf4d91e2
Best regards,
--
Mahadevan P <mahadevan.p@oss.qualcomm.com>
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