[PATCH 0/2] perf riscv: Implement rdtsc()

[PATCH 0/2] perf riscv: Implement rdtsc()

[Chen Pei]

tools/perf falls back to the __weak rdtsc() stub in tools/perf/util/tsc.c
on every architecture that does not override it, riscv included.  The
stub returns a constant 0, so anything that reaches for the counter gets
a value that means nothing and cannot tell it apart from a counter that
happens to be at 0.

The time CSR is a natural TSC equivalent on riscv: readable from user
mode, constant frequency, and the same counter that riscv's
arch_perf_update_userpage() feeds the user page conversion fields from,
ever since commit 83c5e13b8cbb ("riscv: Prepare for user-space perf
event mmap support").  This series registers that on the tools side.

The two patches are split so that the first stands on its own:

1. Implement rdtsc() over the time CSR for riscv.

2. Replace the compile-time TSC support check with a weak
   arch__rdtsc_supported() hook, so that support is declared next to
   the rdtsc() it describes rather than in the central list of compiler
   macros.

What this is worth beyond the subtest result:

1. The subtest is the only reader of those conversion fields riscv
   can run, so it guards arithmetic that has shipped unexercised;
   registering the counter at the same time leaves a future riscv
   auxtrace driver the reading and the conversion already in place.

2. The hook gives a caller something to ask the architecture before
   it uses the counter value, instead of each caller keeping its own
   copy of the macro list.

Tests:
======
- The "Convert perf time to TSC" test in a riscv64 QEMU virt guest
  with sscofpmf: the subtest skips before the series, passes after it.
- With the riscv implementation left out of the build, so that the
  weak defaults are in effect, the subtest still skips: the behaviour
  of an architecture without a counter is unchanged.

Chen Pei (2):
  perf riscv: Implement rdtsc()
  perf tsc: Replace the compile-time TSC support check with a weak hook

 tools/perf/arch/arm64/util/tsc.c    |  5 +++++
 tools/perf/arch/riscv/util/Build    |  1 +
 tools/perf/arch/riscv/util/tsc.c    | 24 ++++++++++++++++++++++++
 tools/perf/arch/x86/util/tsc.c      |  5 +++++
 tools/perf/tests/perf-time-to-tsc.c | 12 +-----------
 tools/perf/util/tsc.c               |  9 +++++++++
 tools/perf/util/tsc.h               |  1 +
 7 files changed, 46 insertions(+), 11 deletions(-)
 create mode 100644 tools/perf/arch/riscv/util/tsc.c

-- 
2.50.1

[PATCH 1/2] perf riscv: Implement rdtsc()

[Chen Pei]

There is no riscv implementation of rdtsc(), so perf links against the
weak stub in util/tsc.c and every caller reads a constant 0 that is
indistinguishable from a real counter standing still.

Implement rdtsc() over the time CSR with rdtime.  The time CSR is a TSC
equivalent on riscv: it is readable from user mode, it ticks at a
constant frequency, and it is the same counter that riscv's
arch_perf_update_userpage() builds the user page conversion fields from,
so the counter and perf time share a timebase.

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
 tools/perf/arch/riscv/util/Build |  1 +
 tools/perf/arch/riscv/util/tsc.c | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 tools/perf/arch/riscv/util/tsc.c

diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build
index 2328fb9a30a3..52cd6a481de8 100644
--- a/tools/perf/arch/riscv/util/Build
+++ b/tools/perf/arch/riscv/util/Build
@@ -1 +1,2 @@
 perf-util-y += header.o
+perf-util-y += tsc.o
diff --git a/tools/perf/arch/riscv/util/tsc.c b/tools/perf/arch/riscv/util/tsc.c
new file mode 100644
index 000000000000..7cc4710ac38c
--- /dev/null
+++ b/tools/perf/arch/riscv/util/tsc.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/types.h>
+
+#include "../../../util/tsc.h"
+
+u64 rdtsc(void)
+{
+	u64 val;
+
+	/*
+	 * The time CSR ticks at a constant frequency and is the same counter
+	 * the kernel feeds into the user page conversion fields through
+	 * sched_clock(), so it is a TSC equivalent here.
+	 */
+	asm volatile("rdtime %0" : "=r" (val));
+
+	return val;
+}
-- 
2.50.1

[PATCH 2/2] perf tsc: Replace the compile-time TSC support check with a weak hook

[Chen Pei]

The "TSC support" subtest of the "Convert perf time to TSC" test decides
whether the architecture is covered by matching compiler macros for
x86_64, i386 and arm64.  That list has to be edited for every new
architecture, and it can drift apart from the set of architectures that
really provide a counter: util/tsc.c already ships a weak rdtsc() which
an architecture overrides with a strong definition when it has one.

Add a weak arch__rdtsc_supported() next to the weak rdtsc(), let the
test query it instead of the macros, and have x86, arm64 and riscv
override it in the file where they implement rdtsc().  Support is then
declared next to the counter it describes, and a caller can tell a stub
apart from a real counter without keeping its own copy of the macro
list.  This follows the pattern of the other optional per-architecture
hooks in util/ such as get_cpuid_str().

x86 and arm64 keep the same behaviour, and riscv starts running the
subtest because it gained rdtsc() in the previous patch.

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
 tools/perf/arch/arm64/util/tsc.c    |  5 +++++
 tools/perf/arch/riscv/util/tsc.c    |  5 +++++
 tools/perf/arch/x86/util/tsc.c      |  5 +++++
 tools/perf/tests/perf-time-to-tsc.c | 12 +-----------
 tools/perf/util/tsc.c               |  9 +++++++++
 tools/perf/util/tsc.h               |  1 +
 6 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/tools/perf/arch/arm64/util/tsc.c b/tools/perf/arch/arm64/util/tsc.c
index cc85bd9e73f1..fd7fba50d0a6 100644
--- a/tools/perf/arch/arm64/util/tsc.c
+++ b/tools/perf/arch/arm64/util/tsc.c
@@ -19,3 +19,8 @@ u64 rdtsc(void)
 
 	return val;
 }
+
+bool arch__rdtsc_supported(void)
+{
+	return true;
+}
diff --git a/tools/perf/arch/riscv/util/tsc.c b/tools/perf/arch/riscv/util/tsc.c
index 7cc4710ac38c..312b0c755439 100644
--- a/tools/perf/arch/riscv/util/tsc.c
+++ b/tools/perf/arch/riscv/util/tsc.c
@@ -17,3 +17,8 @@ u64 rdtsc(void)
 
 	return val;
 }
+
+bool arch__rdtsc_supported(void)
+{
+	return true;
+}
diff --git a/tools/perf/arch/x86/util/tsc.c b/tools/perf/arch/x86/util/tsc.c
index 3a439e4b12d2..6c01e96b5c2e 100644
--- a/tools/perf/arch/x86/util/tsc.c
+++ b/tools/perf/arch/x86/util/tsc.c
@@ -17,6 +17,11 @@ u64 rdtsc(void)
 	return low | ((u64)high) << 32;
 }
 
+bool arch__rdtsc_supported(void)
+{
+	return true;
+}
+
 /*
  * Derive the TSC frequency in Hz from the /proc/cpuinfo, for example:
  * ...
diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c
index f8f71fdd32b1..c91e22d93b53 100644
--- a/tools/perf/tests/perf-time-to-tsc.c
+++ b/tools/perf/tests/perf-time-to-tsc.c
@@ -22,16 +22,6 @@
 #include "tests.h"
 #include "util/sample.h"
 
-/*
- * Except x86_64/i386 and Arm64, other archs don't support TSC in perf.  Just
- * enable the test for x86_64/i386 and Arm64 archs.
- */
-#if defined(__x86_64__) || defined(__i386__) || defined(__aarch64__)
-#define TSC_IS_SUPPORTED 1
-#else
-#define TSC_IS_SUPPORTED 0
-#endif
-
 #define CHECK__(x) {				\
 	while ((x) < 0) {			\
 		pr_debug(#x " failed!\n");	\
@@ -49,7 +39,7 @@
 static int test__tsc_is_supported(struct test_suite *test __maybe_unused,
 				  int subtest __maybe_unused)
 {
-	if (!TSC_IS_SUPPORTED) {
+	if (!arch__rdtsc_supported()) {
 		pr_debug("Test not supported on this architecture\n");
 		return TEST_SKIP;
 	}
diff --git a/tools/perf/util/tsc.c b/tools/perf/util/tsc.c
index ebf289bf6b9d..815621b1d112 100644
--- a/tools/perf/util/tsc.c
+++ b/tools/perf/util/tsc.c
@@ -113,6 +113,15 @@ u64 __weak rdtsc(void)
 	return 0;
 }
 
+/*
+ * An architecture that implements rdtsc() with a real counter should override
+ * this, so that users of the counter can tell a stub apart from support.
+ */
+bool __weak arch__rdtsc_supported(void)
+{
+	return false;
+}
+
 size_t perf_event__fprintf_time_conv(union perf_event *event, FILE *fp)
 {
 	struct perf_record_time_conv *tc = (struct perf_record_time_conv *)event;
diff --git a/tools/perf/util/tsc.h b/tools/perf/util/tsc.h
index 57ce8449647f..83e76b207365 100644
--- a/tools/perf/util/tsc.h
+++ b/tools/perf/util/tsc.h
@@ -25,6 +25,7 @@ int perf_read_tsc_conversion(const struct perf_event_mmap_page *pc,
 u64 perf_time_to_tsc(u64 ns, struct perf_tsc_conversion *tc);
 u64 tsc_to_perf_time(u64 cyc, struct perf_tsc_conversion *tc);
 u64 rdtsc(void);
+bool arch__rdtsc_supported(void);
 u64 arch_get_tsc_freq(void);
 
 size_t perf_event__fprintf_time_conv(union perf_event *event, FILE *fp);
-- 
2.50.1

Re: [PATCH 1/2] perf riscv: Implement rdtsc()

[Anup Patel]

On Mon, Sep 28, 2026 at 3:20 PM Chen Pei <cp0613@linux.alibaba.com> wrote:
>
> There is no riscv implementation of rdtsc(), so perf links against the
> weak stub in util/tsc.c and every caller reads a constant 0 that is
> indistinguishable from a real counter standing still.
>
> Implement rdtsc() over the time CSR with rdtime.  The time CSR is a TSC
> equivalent on riscv: it is readable from user mode, it ticks at a
> constant frequency, and it is the same counter that riscv's
> arch_perf_update_userpage() builds the user page conversion fields from,
> so the counter and perf time share a timebase.
>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>

LGTM from RISC-V perspective.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  tools/perf/arch/riscv/util/Build |  1 +
>  tools/perf/arch/riscv/util/tsc.c | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+)
>  create mode 100644 tools/perf/arch/riscv/util/tsc.c
>
> diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build
> index 2328fb9a30a3..52cd6a481de8 100644
> --- a/tools/perf/arch/riscv/util/Build
> +++ b/tools/perf/arch/riscv/util/Build
> @@ -1 +1,2 @@
>  perf-util-y += header.o
> +perf-util-y += tsc.o
> diff --git a/tools/perf/arch/riscv/util/tsc.c b/tools/perf/arch/riscv/util/tsc.c
> new file mode 100644
> index 000000000000..7cc4710ac38c
> --- /dev/null
> +++ b/tools/perf/arch/riscv/util/tsc.c
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <linux/types.h>
> +
> +#include "../../../util/tsc.h"
> +
> +u64 rdtsc(void)
> +{
> +       u64 val;
> +
> +       /*
> +        * The time CSR ticks at a constant frequency and is the same counter
> +        * the kernel feeds into the user page conversion fields through
> +        * sched_clock(), so it is a TSC equivalent here.
> +        */
> +       asm volatile("rdtime %0" : "=r" (val));
> +
> +       return val;
> +}
> --
> 2.50.1
>
>

Re: [PATCH 2/2] perf tsc: Replace the compile-time TSC support check with a weak hook

[Anup Patel]

On Mon, Sep 28, 2026 at 3:18 PM Chen Pei <cp0613@linux.alibaba.com> wrote:
>
> The "TSC support" subtest of the "Convert perf time to TSC" test decides
> whether the architecture is covered by matching compiler macros for
> x86_64, i386 and arm64.  That list has to be edited for every new
> architecture, and it can drift apart from the set of architectures that
> really provide a counter: util/tsc.c already ships a weak rdtsc() which
> an architecture overrides with a strong definition when it has one.
>
> Add a weak arch__rdtsc_supported() next to the weak rdtsc(), let the
> test query it instead of the macros, and have x86, arm64 and riscv
> override it in the file where they implement rdtsc().  Support is then
> declared next to the counter it describes, and a caller can tell a stub
> apart from a real counter without keeping its own copy of the macro
> list.  This follows the pattern of the other optional per-architecture
> hooks in util/ such as get_cpuid_str().
>
> x86 and arm64 keep the same behaviour, and riscv starts running the
> subtest because it gained rdtsc() in the previous patch.
>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>

LGTM from RISC-V perspective.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  tools/perf/arch/arm64/util/tsc.c    |  5 +++++
>  tools/perf/arch/riscv/util/tsc.c    |  5 +++++
>  tools/perf/arch/x86/util/tsc.c      |  5 +++++
>  tools/perf/tests/perf-time-to-tsc.c | 12 +-----------
>  tools/perf/util/tsc.c               |  9 +++++++++
>  tools/perf/util/tsc.h               |  1 +
>  6 files changed, 26 insertions(+), 11 deletions(-)
>
> diff --git a/tools/perf/arch/arm64/util/tsc.c b/tools/perf/arch/arm64/util/tsc.c
> index cc85bd9e73f1..fd7fba50d0a6 100644
> --- a/tools/perf/arch/arm64/util/tsc.c
> +++ b/tools/perf/arch/arm64/util/tsc.c
> @@ -19,3 +19,8 @@ u64 rdtsc(void)
>
>         return val;
>  }
> +
> +bool arch__rdtsc_supported(void)
> +{
> +       return true;
> +}
> diff --git a/tools/perf/arch/riscv/util/tsc.c b/tools/perf/arch/riscv/util/tsc.c
> index 7cc4710ac38c..312b0c755439 100644
> --- a/tools/perf/arch/riscv/util/tsc.c
> +++ b/tools/perf/arch/riscv/util/tsc.c
> @@ -17,3 +17,8 @@ u64 rdtsc(void)
>
>         return val;
>  }
> +
> +bool arch__rdtsc_supported(void)
> +{
> +       return true;
> +}
> diff --git a/tools/perf/arch/x86/util/tsc.c b/tools/perf/arch/x86/util/tsc.c
> index 3a439e4b12d2..6c01e96b5c2e 100644
> --- a/tools/perf/arch/x86/util/tsc.c
> +++ b/tools/perf/arch/x86/util/tsc.c
> @@ -17,6 +17,11 @@ u64 rdtsc(void)
>         return low | ((u64)high) << 32;
>  }
>
> +bool arch__rdtsc_supported(void)
> +{
> +       return true;
> +}
> +
>  /*
>   * Derive the TSC frequency in Hz from the /proc/cpuinfo, for example:
>   * ...
> diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c
> index f8f71fdd32b1..c91e22d93b53 100644
> --- a/tools/perf/tests/perf-time-to-tsc.c
> +++ b/tools/perf/tests/perf-time-to-tsc.c
> @@ -22,16 +22,6 @@
>  #include "tests.h"
>  #include "util/sample.h"
>
> -/*
> - * Except x86_64/i386 and Arm64, other archs don't support TSC in perf.  Just
> - * enable the test for x86_64/i386 and Arm64 archs.
> - */
> -#if defined(__x86_64__) || defined(__i386__) || defined(__aarch64__)
> -#define TSC_IS_SUPPORTED 1
> -#else
> -#define TSC_IS_SUPPORTED 0
> -#endif
> -
>  #define CHECK__(x) {                           \
>         while ((x) < 0) {                       \
>                 pr_debug(#x " failed!\n");      \
> @@ -49,7 +39,7 @@
>  static int test__tsc_is_supported(struct test_suite *test __maybe_unused,
>                                   int subtest __maybe_unused)
>  {
> -       if (!TSC_IS_SUPPORTED) {
> +       if (!arch__rdtsc_supported()) {
>                 pr_debug("Test not supported on this architecture\n");
>                 return TEST_SKIP;
>         }
> diff --git a/tools/perf/util/tsc.c b/tools/perf/util/tsc.c
> index ebf289bf6b9d..815621b1d112 100644
> --- a/tools/perf/util/tsc.c
> +++ b/tools/perf/util/tsc.c
> @@ -113,6 +113,15 @@ u64 __weak rdtsc(void)
>         return 0;
>  }
>
> +/*
> + * An architecture that implements rdtsc() with a real counter should override
> + * this, so that users of the counter can tell a stub apart from support.
> + */
> +bool __weak arch__rdtsc_supported(void)
> +{
> +       return false;
> +}
> +
>  size_t perf_event__fprintf_time_conv(union perf_event *event, FILE *fp)
>  {
>         struct perf_record_time_conv *tc = (struct perf_record_time_conv *)event;
> diff --git a/tools/perf/util/tsc.h b/tools/perf/util/tsc.h
> index 57ce8449647f..83e76b207365 100644
> --- a/tools/perf/util/tsc.h
> +++ b/tools/perf/util/tsc.h
> @@ -25,6 +25,7 @@ int perf_read_tsc_conversion(const struct perf_event_mmap_page *pc,
>  u64 perf_time_to_tsc(u64 ns, struct perf_tsc_conversion *tc);
>  u64 tsc_to_perf_time(u64 cyc, struct perf_tsc_conversion *tc);
>  u64 rdtsc(void);
> +bool arch__rdtsc_supported(void);
>  u64 arch_get_tsc_freq(void);
>
>  size_t perf_event__fprintf_time_conv(union perf_event *event, FILE *fp);
> --
> 2.50.1
>
>

Re: [PATCH 2/2] perf tsc: Replace the compile-time TSC support check with a weak hook

[Leo Yan]

On Mon, Sep 28, 2026 at 05:47:39PM +0800, Chen Pei wrote:

[...]

> Add a weak arch__rdtsc_supported() next to the weak rdtsc(), let the
> test query it instead of the macros, and have x86, arm64 and riscv
> override it in the file where they implement rdtsc().

The patch itself is fine for me.

Just a bit on refactoring. You could refer to the implementation of
PERF_HAVE_JITDUMP in arch Makefile and "CFLAGS += -DHAVE_JITDUMP" and
do similiar thing for rdtsc.

Seems to me, we can just use build system for configurations.

Thanks,
Leo