[PATCH 0/7] NVMe support for Apple M3, M3 Pro and M3 Max/Ultra devices

[PATCH 0/7] NVMe support for Apple M3, M3 Pro and M3 Max/Ultra devices

[Janne Grunau]

Hej,

this series adds NVMe support to all M3, M3 Pro and M3 Max/Ultra
devices. The hardware works the same way as T602x (M2 Pro/Max/Ultra). If
there were changes they don't affect the way the existing Linux drivers
use the hardware. So this series adds new per-SoC compatible strings to
the mailbox, SART (IOMMU) and ANS (NVMe host controller) bindings and
the device nodes.

Merge strategy:
The nvme tree has "dt-bindings: nvme: Add apple,t8132-nvme-ans2
compatible" [1] queued for apple,nvme-ans.yaml so "dt-bindings:
nvme: apple: Add Apple M3 compatibles" should go through the nvme tree
as well. The MAINTAINERS update can go with it.
The other dt-binding changes are trivial so there is a slight preference
to take them to the apple-soc tree with Acked-by: by their maintainers.
This keeps the number of `make dtbs_check` warnings in the apple-soc
tree low. Merging them through their maintainer's trees is not a
problem either.
The apple device tree changes are based on / depend on commit
eea4f3b5e9e1 ("Merge patch series "dt-check-style strict fixes for Apple
M3, M3 Pro/Max/Ultra"") apple-soc/dt-7.4.

I intentionally omitted the Fixes: in the MAINTAINERS update as I don't
see any value in adding this change to stable releases.

Link: https://lore.kernel.org/asahi/20260906-apple-nvme-t8132-v2-0-ac0328590823@cyberchaos.dev/ [1]

Signed-off-by: Janne Grunau <j@jannau.net>
---
Janne Grunau (5):
      MAINTAINERS: Add NVMe devicetree bindings
      dt-bindings: mailbox: Add Apple M3 compatibles
      dt-bindings: nvme: apple,nvme-ans: Add Apple M3 compatibles
      arm64: dts: apple: t6030: Add NVMe device nodes
      arm64: dts: apple: t6031: Add NVMe device nodes

Michael Reeves (2):
      dt-bindings: iommu: apple,sart: Add Apple M3 compatibles
      arm64: dts: apple: t8122: Add NVMe device nodes

 .../devicetree/bindings/iommu/apple,sart.yaml      |  3 ++
 .../devicetree/bindings/mailbox/apple,mailbox.yaml |  3 ++
 .../devicetree/bindings/nvme/apple,nvme-ans.yaml   |  7 +++-
 MAINTAINERS                                        |  1 +
 arch/arm64/boot/dts/apple/t6030.dtsi               | 42 ++++++++++++++++++++
 arch/arm64/boot/dts/apple/t6031-nvme.dtsi          | 46 ++++++++++++++++++++++
 arch/arm64/boot/dts/apple/t6031.dtsi               |  1 +
 arch/arm64/boot/dts/apple/t6032.dtsi               |  1 +
 arch/arm64/boot/dts/apple/t8122.dtsi               | 40 +++++++++++++++++++
 9 files changed, 143 insertions(+), 1 deletion(-)
---
base-commit: eea4f3b5e9e19389af3b99af64cdf7352b67c298
change-id: 20260924-apple-m3-nvme-87d8a0a7ed91

Best regards,
--  
Janne Grunau <j@jannau.net>

[PATCH 1/7] MAINTAINERS: Add NVMe devicetree bindings

[Janne Grunau]

Commit 82b96552f15a ("dt-bindings: nvme: Add Apple ANS NVMe") added only
the Apple bindings file to the apple-soc MAINTAINERS entry but did not
add the directory to the NVMe driver entry.
The apple driver is the only driver requiring dt-bindings and might
remain the only one so this shouldn't have caused issues.

Signed-off-by: Janne Grunau <j@jannau.net>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3a19da74d00c..6f9d1736d13f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19578,6 +19578,7 @@ W:	http://git.infradead.org/nvme.git
 T:	git git://git.infradead.org/nvme.git
 F:	Documentation/ABI/stable/sysfs-nvme
 F:	Documentation/admin-guide/nvme-multipath.rst
+F:	Documentation/devicetree/bindings/nvme/
 F:	Documentation/fault-injection/nvme-fault-injection.rst
 F:	Documentation/nvme/
 F:	drivers/nvme/common/

-- 
2.55.0

[PATCH 2/7] dt-bindings: mailbox: Add Apple M3 compatibles

[Janne Grunau]

The ASC mailbox on Apple M3, M3 Pro and M3 Max/Ultra is compatible to
the mailbox on M1 ("apple,asc-mailbox-v4"). Add their per-SoC
compatibles "apple,t8122-asc-mailbox", "apple,t6030-asc-mailbox" and
"apple,t6031-asc-mailbox" to its dt-bindings.

Signed-off-by: Janne Grunau <j@jannau.net>
---
 Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
index 28985cc62c25..9a6dfb0b2f28 100644
--- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
@@ -30,8 +30,11 @@ properties:
           - enum:
               - apple,t8103-asc-mailbox
               - apple,t8112-asc-mailbox
+              - apple,t8122-asc-mailbox
               - apple,t6000-asc-mailbox
               - apple,t6020-asc-mailbox
+              - apple,t6030-asc-mailbox
+              - apple,t6031-asc-mailbox
           - const: apple,asc-mailbox-v4
 
       - description:

-- 
2.55.0

[PATCH 3/7] dt-bindings: iommu: apple,sart: Add Apple M3 compatibles

[Janne Grunau]

From: Michael Reeves <michael.reeves077@gmail.com>

SART on M3, M3 Pro and M3 Max/Ultra is compatible to SART on M1
Pro/Max/Ultra. Add their per-SoC compatibles "apple,t8122-sart",
"apple,t6030-sart" and "apple,t6031-sart" to its dt-bindings.

Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
Signed-off-by: Janne Grunau <j@jannau.net>
---
 Documentation/devicetree/bindings/iommu/apple,sart.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/apple,sart.yaml b/Documentation/devicetree/bindings/iommu/apple,sart.yaml
index 88e66d4b13c6..015158a9676b 100644
--- a/Documentation/devicetree/bindings/iommu/apple,sart.yaml
+++ b/Documentation/devicetree/bindings/iommu/apple,sart.yaml
@@ -32,7 +32,10 @@ properties:
       - items:
           - enum:
               - apple,t6020-sart
+              - apple,t6030-sart
+              - apple,t6031-sart
               - apple,t8112-sart
+              - apple,t8122-sart
           - const: apple,t6000-sart
       - enum:
           - apple,t6000-sart

-- 
2.55.0

[PATCH 4/7] dt-bindings: nvme: apple,nvme-ans: Add Apple M3 compatibles

[Janne Grunau]

The ANS NVMe on Apple M3, M3 Pro and M3 Max/Ultra is compatible with
with the NVMe on M1. Add their per-SoC compatibles
"apple,t8122-nvme-ans2", "apple,t6030-nvme-ans2" and
"apple,t6031-nvme-ans2" to its dt-bindings.
The NVMe on M3 Max/Ultra uses 3 power-domains so add it to the
power-domains conditional to change 'minItems'.

Signed-off-by: Janne Grunau <j@jannau.net>
---
 Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml
index 4c0b1f90aff8..10ca8cc5f52a 100644
--- a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml
+++ b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml
@@ -14,7 +14,11 @@ properties:
     oneOf:
       - const: apple,t8015-nvme-ans2
       - items:
-          - const: apple,t6020-nvme-ans2
+          - enum:
+              - apple,t6020-nvme-ans2
+              - apple,t6030-nvme-ans2
+              - apple,t6031-nvme-ans2
+              - apple,t8122-nvme-ans2
           - const: apple,t8103-nvme-ans2
       - items:
           - enum:
@@ -75,6 +79,7 @@ if:
         enum:
           - apple,t6000-nvme-ans2
           - apple,t6020-nvme-ans2
+          - apple,t6031-nvme-ans2
 then:
   properties:
     power-domains:

-- 
2.55.0

[PATCH 5/7] arm64: dts: apple: t6030: Add NVMe device nodes

[Janne Grunau]

Apple silicon SoCs have a built-in NVMe host controller. Using it
requires device nodes for its IOMMU (SART), its mailbox and the ANS
coprocessor implementing the NVMe host controller.

Signed-off-by: Janne Grunau <j@jannau.net>
---
 arch/arm64/boot/dts/apple/t6030.dtsi | 42 ++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t6030.dtsi b/arch/arm64/boot/dts/apple/t6030.dtsi
index 524e532830e2..85a16d03e22f 100644
--- a/arch/arm64/boot/dts/apple/t6030.dtsi
+++ b/arch/arm64/boot/dts/apple/t6030.dtsi
@@ -537,6 +537,48 @@ pinctrl_aop: pinctrl@374824000 {
 
 			apple,npins = <54>;
 		};
+
+		ans_mbox: mbox@389408000 {
+			compatible = "apple,t6030-asc-mailbox",
+				     "apple,asc-mailbox-v4";
+			reg = <0x3 0x89408000 0x0 0x4000>;
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 839 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 840 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 841 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 842 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "send-empty", "send-not-empty",
+					  "recv-empty", "recv-not-empty";
+
+			#mbox-cells = <0>;
+			power-domains = <&ps_ans>;
+		};
+
+		sart: sart@38dc50000 {
+			compatible = "apple,t6030-sart", "apple,t6000-sart";
+			reg = <0x3 0x8dc50000 0x0 0xc000>;
+			power-domains = <&ps_ans>;
+		};
+
+		nvme: nvme@38dcc0000 {
+			compatible = "apple,t6030-nvme-ans2",
+				     "apple,t8103-nvme-ans2";
+			reg = <0x3 0x8dcc0000 0x0 0x60000>,
+			      <0x3 0x89400000 0x0 0x4000>;
+			reg-names = "nvme", "ans";
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 851 IRQ_TYPE_LEVEL_HIGH>;
+
+			mboxes = <&ans_mbox>;
+
+			power-domains = <&ps_ans>, <&ps_apcie_sys_st>;
+			power-domain-names = "ans", "apcie0";
+			resets = <&ps_ans>;
+
+			apple,sart = <&sart>;
+		};
 	};
 
 	timer {

-- 
2.55.0

[PATCH 6/7] arm64: dts: apple: t6031: Add NVMe device nodes

[Janne Grunau]

Apple silicon SoCs have a built-in NVMe host controller. Using it
requires device nodes for its IOMMU (SART), its mailbox and the ANS
coprocessor implementing the NVMe host controller.
Since the NAND chips on the M3 Ultra are connected to its second die use
t6031-nvme.dtsi for the NVMe device nodes.

Signed-off-by: Janne Grunau <j@jannau.net>
---
 arch/arm64/boot/dts/apple/t6031-nvme.dtsi | 46 +++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/apple/t6031.dtsi      |  1 +
 arch/arm64/boot/dts/apple/t6032.dtsi      |  1 +
 3 files changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t6031-nvme.dtsi b/arch/arm64/boot/dts/apple/t6031-nvme.dtsi
new file mode 100644
index 000000000000..d3831bbc2bf2
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6031-nvme.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * NVMe related devices for Apple T603x SoCs.
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+&SOC_NODE {
+	DIE_NODE(ans_mbox): mbox@349408000 {
+		compatible = "apple,t6031-asc-mailbox", "apple,asc-mailbox-v4";
+		reg = <0x3 0x49408000 0x0 0x4000>;
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_IRQ DIE_NO 1274 IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_IRQ DIE_NO 1275 IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_IRQ DIE_NO 1276 IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_IRQ DIE_NO 1277 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "send-empty", "send-not-empty",
+				  "recv-empty", "recv-not-empty";
+		#mbox-cells = <0>;
+		power-domains = <&DIE_NODE(ps_ans)>;
+	};
+
+	DIE_NODE(sart): sart@34dc50000 {
+		compatible = "apple,t6031-sart", "apple,t6000-sart";
+		reg = <0x3 0x4dc50000 0x0 0x10000>;
+		power-domains = <&DIE_NODE(ps_ans)>;
+	};
+
+	DIE_NODE(nvme): nvme@34dcc0000 {
+		compatible = "apple,t6031-nvme-ans2", "apple,t8103-nvme-ans2";
+		reg = <0x3 0x4dcc0000 0x0 0x40000>,
+		      <0x3 0x49400000 0x0 0x4000>;
+		reg-names = "nvme", "ans";
+		interrupt-parent = <&aic>;
+		/* The NVME interrupt is always routed to die 0 */
+		interrupts = <AIC_IRQ 0 2366 IRQ_TYPE_LEVEL_HIGH>;
+		mboxes = <&DIE_NODE(ans_mbox)>;
+		power-domains = <&DIE_NODE(ps_ans)>,
+				<&DIE_NODE(ps_apcie_sys_st)>,
+				<&DIE_NODE(ps_apcie_sys_st1)>;
+		power-domain-names = "ans", "apcie0", "apcie1";
+		resets = <&DIE_NODE(ps_ans)>;
+
+		apple,sart = <&DIE_NODE(sart)>;
+	};
+};
diff --git a/arch/arm64/boot/dts/apple/t6031.dtsi b/arch/arm64/boot/dts/apple/t6031.dtsi
index a2aa64ea9db9..30a91c1a47d2 100644
--- a/arch/arm64/boot/dts/apple/t6031.dtsi
+++ b/arch/arm64/boot/dts/apple/t6031.dtsi
@@ -39,6 +39,7 @@ soc: soc {
 #include "t6031-die0.dtsi"
 #include "t6031-dieX.dtsi"
 #include "t6031-gpio-pins.dtsi"
+#include "t6031-nvme.dtsi"
 #include "t6031-pmgr.dtsi"
 
 #undef DIE
diff --git a/arch/arm64/boot/dts/apple/t6032.dtsi b/arch/arm64/boot/dts/apple/t6032.dtsi
index efe56d2a9a79..2a3a1fed59df 100644
--- a/arch/arm64/boot/dts/apple/t6032.dtsi
+++ b/arch/arm64/boot/dts/apple/t6032.dtsi
@@ -362,6 +362,7 @@ die1: soc@2200000000 {
 #define SOC_NODE die1
 
 #include "t6031-dieX.dtsi"
+#include "t6031-nvme.dtsi"
 #include "t6031-pmgr.dtsi"
 
 /delete-node/ &ps_pmp_die1;

-- 
2.55.0

[PATCH 7/7] arm64: dts: apple: t8122: Add NVMe device nodes

[Janne Grunau]

From: Michael Reeves <michael.reeves077@gmail.com>

On Apple Silicon, NVMe communication is mediated by a
coprocessor known as the ANS, and protected by its own
IOMMU known as the SART.

Add the following nodes to the M3 (t8122) device tree:
- Mailbox for the ANS coprocessor
- SART (IOMMU for the ANS coprocessor)
- The NVMe / ANS coprocessor itself

Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
Signed-off-by: Janne Grunau <j@jannau.net>
---
 arch/arm64/boot/dts/apple/t8122.dtsi | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t8122.dtsi b/arch/arm64/boot/dts/apple/t8122.dtsi
index 52257fa22631..959ddf36efa1 100644
--- a/arch/arm64/boot/dts/apple/t8122.dtsi
+++ b/arch/arm64/boot/dts/apple/t8122.dtsi
@@ -454,6 +454,46 @@ pinctrl_aop: pinctrl@2f4824000 {
 
 			apple,npins = <54>;
 		};
+
+		ans_mbox: mbox@309408000 {
+			compatible = "apple,t8122-asc-mailbox",
+				     "apple,asc-mailbox-v4";
+			reg = <0x3 0x09408000 0x0 0x4000>;
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 730 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 731 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 732 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 733 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "send-empty", "send-not-empty",
+					  "recv-empty", "recv-not-empty";
+
+			#mbox-cells = <0>;
+			power-domains = <&ps_ans>;
+		};
+
+		sart: sart@30dc50000 {
+			compatible = "apple,t8122-sart", "apple,t6000-sart";
+			reg = <0x3 0x0dc50000 0x0 0x10000>;
+			power-domains = <&ps_ans>;
+		};
+
+		nvme: nvme@30dcc0000 {
+			compatible = "apple,t8122-nvme-ans2",
+				     "apple,t8103-nvme-ans2";
+			reg = <0x3 0x0dcc0000 0x0 0x60000>,
+			      <0x3 0x09400000 0x0 0x4000>;
+			reg-names = "nvme", "ans";
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 742 IRQ_TYPE_LEVEL_HIGH>;
+			mboxes = <&ans_mbox>;
+			power-domains = <&ps_ans>, <&ps_apcie_st>;
+			power-domain-names = "ans", "apcie0";
+			resets = <&ps_ans>;
+
+			apple,sart = <&sart>;
+		};
 	};
 
 	timer {

-- 
2.55.0

Re: [PATCH 2/7] dt-bindings: mailbox: Add Apple M3 compatibles

[Krzysztof Kozlowski]

On Fri, Sep 25, 2026 at 10:22:49AM +0200, Janne Grunau wrote:
> The ASC mailbox on Apple M3, M3 Pro and M3 Max/Ultra is compatible to
> the mailbox on M1 ("apple,asc-mailbox-v4"). Add their per-SoC
> compatibles "apple,t8122-asc-mailbox", "apple,t6030-asc-mailbox" and
> "apple,t6031-asc-mailbox" to its dt-bindings.
> 
> Signed-off-by: Janne Grunau <j@jannau.net>
> ---
>  Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 3 +++
>  1 file changed, 3 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 3/7] dt-bindings: iommu: apple,sart: Add Apple M3 compatibles

[Krzysztof Kozlowski]

On Fri, Sep 25, 2026 at 10:22:50AM +0200, Janne Grunau wrote:
> From: Michael Reeves <michael.reeves077@gmail.com>
> 
> SART on M3, M3 Pro and M3 Max/Ultra is compatible to SART on M1
> Pro/Max/Ultra. Add their per-SoC compatibles "apple,t8122-sart",
> "apple,t6030-sart" and "apple,t6031-sart" to its dt-bindings.
> 
> Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
> Signed-off-by: Janne Grunau <j@jannau.net>
> ---
>  Documentation/devicetree/bindings/iommu/apple,sart.yaml | 3 +++
>  1 file changed, 3 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 4/7] dt-bindings: nvme: apple,nvme-ans: Add Apple M3 compatibles

[Krzysztof Kozlowski]

On Fri, Sep 25, 2026 at 10:22:51AM +0200, Janne Grunau wrote:
> The ANS NVMe on Apple M3, M3 Pro and M3 Max/Ultra is compatible with
> with the NVMe on M1. Add their per-SoC compatibles
> "apple,t8122-nvme-ans2", "apple,t6030-nvme-ans2" and
> "apple,t6031-nvme-ans2" to its dt-bindings.
> The NVMe on M3 Max/Ultra uses 3 power-domains so add it to the
> power-domains conditional to change 'minItems'.
> 
> Signed-off-by: Janne Grunau <j@jannau.net>
> ---
>  Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 2/7] dt-bindings: mailbox: Add Apple M3 compatibles

[Luna Jernberg]

https://youtu.be/TPwe53kCJuM

Den tis 29 sep. 2026 kl 10:21 skrev Krzysztof Kozlowski <krzk@kernel.org>:
>
> On Fri, Sep 25, 2026 at 10:22:49AM +0200, Janne Grunau wrote:
> > The ASC mailbox on Apple M3, M3 Pro and M3 Max/Ultra is compatible to
> > the mailbox on M1 ("apple,asc-mailbox-v4"). Add their per-SoC
> > compatibles "apple,t8122-asc-mailbox", "apple,t6030-asc-mailbox" and
> > "apple,t6031-asc-mailbox" to its dt-bindings.
> >
> > Signed-off-by: Janne Grunau <j@jannau.net>
> > ---
> >  Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 3 +++
> >  1 file changed, 3 insertions(+)
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> Best regards,
> Krzysztof
>
>

Re: [PATCH 2/7] dt-bindings: mailbox: Add Apple M3 compatibles

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 955 bytes --]

On Tue, Sep 29, 2026 at 03:22:09PM +0200, Luna Jernberg wrote:
> https://youtu.be/TPwe53kCJuM

Why are you linking this here? Is there something relevant to this
series in that stream?

Confused,
Conor.

> 
> Den tis 29 sep. 2026 kl 10:21 skrev Krzysztof Kozlowski <krzk@kernel.org>:
> >
> > On Fri, Sep 25, 2026 at 10:22:49AM +0200, Janne Grunau wrote:
> > > The ASC mailbox on Apple M3, M3 Pro and M3 Max/Ultra is compatible to
> > > the mailbox on M1 ("apple,asc-mailbox-v4"). Add their per-SoC
> > > compatibles "apple,t8122-asc-mailbox", "apple,t6030-asc-mailbox" and
> > > "apple,t6031-asc-mailbox" to its dt-bindings.
> > >
> > > Signed-off-by: Janne Grunau <j@jannau.net>
> > > ---
> > >  Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 3 +++
> > >  1 file changed, 3 insertions(+)
> >
> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> >
> > Best regards,
> > Krzysztof
> >
> >

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