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* [PATCH v7 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus
@ 2026-09-29 16:54 Andrea Righi
  2026-09-29 16:54 ` [PATCH 1/2] sched/fair: Honor asymmetric SMT priority in idle selection Andrea Righi
  2026-09-29 16:54 ` [PATCH 2/2] sched/topology: Add asymmetric SMT packing override Andrea Righi
  0 siblings, 2 replies; 3+ messages in thread
From: Andrea Righi @ 2026-09-29 16:54 UTC (permalink / raw)
  To: Ingo Molnar, Peter Zijlstra, Juri Lelli, Vincent Guittot, Will Deacon
  Cc: Dietmar Eggemann, Steven Rostedt, Ben Segall, Mel Gorman,
	Valentin Schneider, K Prateek Nayak, Christian Loehle,
	Srikar Dronamraju, Shrikanth Hegde, Phil Auld, Breno Leitao,
	Jonathan Corbet, Shuah Khan, Randy Dunlap, Lee Trager,
	Vikram Sethi, Kayra Cizmeci, linux-doc, linux-kernel

NVIDIA Olympus implements SMT with two symmetric processing elements (PEs).
When only one PE is active, the core operates in single-thread mode and that
PE can use the full core resources. When both PEs are active, the core
operates in two-thread mode and the PEs share those resources. Olympus is
particularly sensitive to brief sibling activations because returning to
single-thread mode after a sibling becomes idle is not immediate. As
described by commit 293f9611ae735 ("sched/fair: Prefer fully idle cores
for NOHZ balancing"):

  Briefly activating an otherwise idle sibling can reduce the
  performance available to the other sibling and this effect does not
  necessarily end once the activated sibling becomes idle: after the ILB
  finishes and its CPU enters WFI, full single-thread performance is
  restored only after the sibling has remained idle for a qualification
  interval (10 Ki cycles on the tested Vera system).

That change prevents the NOHZ idle load balancer from unnecessarily waking
a sibling of a busy PE. However, ordinary task placement can still select
either sibling of an idle core. Repeatedly changing the active PE can keep
Olympus cores in two-thread mode despite little useful overlap between the
siblings.

The first patch teaches the fair scheduler's idle-selection paths to honor
SD_ASYM_PACKING at the shared-capacity SMT level. The scheduler first
selects a candidate CPU and core according to its existing placement and
capacity rules, then chooses the highest-priority available sibling within
that core. POWER7 already enables SD_ASYM_PACKING on its SMT domain through
the PowerPC CPU_FTR_ASYM_SMT feature selected for that processor. The first
patch also applies POWER7's existing hardware-thread order during idle
selection.

Olympus firmware does not currently provide an interface to describe the
preferred SMT sibling. Adding such a firmware or ACPI interface will take
time and will not help systems with existing firmware. Inferring the policy
from MIDR would encode a platform-specific decision in the kernel and make
it harder to replace with a firmware ABI.

The second patch adds sched_smt_asym_packing=on as an explicit fallback for
systems that need SMT asymmetric packing but cannot describe the preference
through firmware. The option adds SD_ASYM_PACKING to the SMT scheduling
domain; omitting it preserves the topology supplied by the architecture or
firmware. Priority remains defined by arch_asym_cpu_priority(). The weak
default prefers lower-numbered logical CPUs, while architecture overrides
remain authoritative and equal-priority siblings remain unordered.

On the tested Olympus system, the lower-numbered logical CPU of each core
is PE0. The preference does not identify a faster PE: PE0 and PE1 have
equal steady-state capacity. Consistently selecting the same sibling avoids
alternating the active PE across wakeups, gives the other sibling more time
idle, and allows more cores to remain in, or return to, full-resource
single-thread mode.

The sched_smt_asym_packing=on path, unchanged from v6, was tested on a
two-node Vera system using 88-thread single-precision GEMM workloads on
the 88 physical cores of NUMA node 0, with both siblings of each core
eligible. Each result below covers five runs. OpenBLAS was evaluated with
its public benchmark/sgemm.goto single-GEMM benchmark. NVIDIA Performance
Libraries (NVPL) was evaluated with a timed benchblas GEMM run. Both used
M=N=K=16384; NVPL used non-transposed inputs, alpha=1, and beta=0.

OpenBLAS throughput increased from 7.11876 +/- 0.06734 TFLOP/s on the
baseline kernel to 7.34669 +/- 0.01936 TFLOP/s with this series (+3.20%).
NVPL throughput increased from 9.64742 +/- 0.17311 TFLOP/s to
10.29695 +/- 0.01786 TFLOP/s (+6.73%). The lower standard deviation also
shows that the results became more predictable. With the series applied,
the workloads consistently settled on the lower-numbered sibling.

Changes in v7:
 - Accept only sched_smt_asym_packing=on, drop the redundant auto and off
   modes (Vincent Guittot, Shrikanth Hegde).
 - Link to v6: https://lore.kernel.org/r/20260917140707.3807229-1-arighi@nvidia.com

Changes in v6:
 - Drop the arm64 MIDR-based enablement and arch_asym_cpu_priority()
   override (Will Deacon).
 - Add the generic sched_smt_asym_packing={auto,on,off} boot option.
 - Use the default -cpu priority ordering instead of interpreting MPIDR.
 - Drop the SMT-specific asymmetric-packing static key and use
   sched_smt_active() (Vincent Guittot).
 - Link to v5: https://lore.kernel.org/r/20260909062649.469633-1-arighi@nvidia.com

Changes in v5:
 - Remove the redundant olympus_prefer_pe0 state (K Prateek Nayak).
 - Link to v4: https://lore.kernel.org/r/20260908082345.103087-1-arighi@nvidia.com

Changes in v4:
 - Honor the SMT sibling priority in the slow path (Srikar Dronamraju).
 - Rename the consolidated helper to select_idle_smt_cpu()
   (Srikar Dronamraju).
 - Link to v3: https://lore.kernel.org/r/20260907163513.4172411-1-arighi@nvidia.com

Changes in v3:
 - Consolidate the SMT-priority adjustment in select_idle_sibling()
   after an idle candidate has been selected (K Prateek Nayak).
 - Fold the asym SMT checks into select_idle_smt_priority() and scan the
   scheduling-domain span directly (K Prateek Nayak).
 - Link to v2: https://lore.kernel.org/r/20260904091838.3617894-1-arighi@nvidia.com

Changes in v2:
 - Clarify that the generic scheduler change also covers POWER7
   (Dietmar Eggemann).
 - Simplify sched_smt_asym_prefer() by inspecting the lowest scheduling
   domain directly (Dietmar Eggemann).
 - Link to v1: https://lore.kernel.org/r/20260831181800.1668646-1-arighi@nvidia.com

Andrea Righi (2):
      sched/fair: Honor asymmetric SMT priority in idle selection
      sched/topology: Add asymmetric SMT packing override

 Documentation/admin-guide/kernel-parameters.txt | 12 ++++
 kernel/sched/fair.c                             | 85 ++++++++++++++++++++-----
 kernel/sched/topology.c                         | 18 ++++++
 3 files changed, 98 insertions(+), 17 deletions(-)

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2026-09-29 16:54 [PATCH v7 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus Andrea Righi
2026-09-29 16:54 ` [PATCH 1/2] sched/fair: Honor asymmetric SMT priority in idle selection Andrea Righi
2026-09-29 16:54 ` [PATCH 2/2] sched/topology: Add asymmetric SMT packing override Andrea Righi

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