From: Divyamani Tripathi <divyamani.tripathi@intel.com>
To: linux-kernel@vger.kernel.org
Cc: sakari.ailus@linux.intel.com, antti.laakso@linux.intel.com,
sarang.sapre@intel.com, manik.bajpai@intel.com,
Divyamani Tripathi <divyamani.tripathi@intel.com>
Subject: [PATCH 6/7] media: ipu6: add IPU8 psys MMU table and PLL power sequencing
Date: Wed, 30 Sep 2026 12:01:47 +0300 [thread overview]
Message-ID: <20260930090148.3980652-7-divyamani.tripathi@intel.com> (raw)
In-Reply-To: <20260930090148.3980652-1-divyamani.tripathi@intel.com>
Port the remaining IPU8 psys platform enablement that already exists
upstream in staging ipu7: the psys MMU hardware table and PLL
request/release in the shared power-on/off path. This driver has no
psys pipeline consumer, so it only affects the psys bus device's power
sequencing and MMU setup.
Signed-off-by: Divyamani Tripathi <divyamani.tripathi@intel.com>
---
drivers/media/pci/intel/ipu6/ipu6-buttress.c | 17 +++
.../intel/ipu6/ipu6-platform-buttress-regs.h | 4 +
drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c | 131 +++++++++++++++++-
drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h | 51 +++++++
4 files changed, 196 insertions(+), 7 deletions(-)
diff --git a/drivers/media/pci/intel/ipu6/ipu6-buttress.c b/drivers/media/pci/intel/ipu6/ipu6-buttress.c
index be07d33a4dab..00d504647c29 100644
--- a/drivers/media/pci/intel/ipu6/ipu6-buttress.c
+++ b/drivers/media/pci/intel/ipu6/ipu6-buttress.c
@@ -512,6 +512,17 @@ static int __ipu7_power_on(struct device *dev,
ipu7_nde_control(isp, true);
}
+ /* IPU8 psys needs its PLL running above 400MHz. */
+ if (!is_isys && IS_IPU8(isp) && ctrl->ratio > IPU8_PS_FREQ_CTL_DEFAULT_RATIO) {
+ writel(1, isp->base + IPU7_BUTTRESS_REG_PS_PLL_ENABLE);
+ ret = readl_poll_timeout(isp->base + IPU7_BUTTRESS_REG_SLEEP_LEVEL_STS,
+ val, (val & IPU7_BUTTRESS_OWN_ACK_PS_CLK),
+ 100, BUTTRESS_POWER_TIMEOUT_US);
+ if (ret)
+ dev_warn(&isp->pdev->dev,
+ "ps_pll req ack timeout: 0x%x\n", val);
+ }
+
/* Request clock ownership. */
ovrd_clk = is_isys ? IPU7_BUTTRESS_OVERRIDE_IS_CLK :
IPU7_BUTTRESS_OVERRIDE_PS_CLK;
@@ -569,6 +580,12 @@ static int __ipu7_power_off(struct device *dev,
ipu7_nde_control(isp, false);
}
+ if (ctrl->subsys_id == IPU_PSYS && IS_IPU8(isp)) {
+ val = readl(isp->base + IPU7_BUTTRESS_REG_SLEEP_LEVEL_STS);
+ if (val & IPU7_BUTTRESS_OWN_ACK_PS_CLK)
+ writel(0, isp->base + IPU7_BUTTRESS_REG_PS_PLL_ENABLE);
+ }
+
return 0;
}
diff --git a/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h b/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h
index a1e00965ac4a..04d196c49c60 100644
--- a/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h
+++ b/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h
@@ -282,6 +282,9 @@ enum {
#define IPU7_BUTTRESS_IS_FREQ_CTL_RATIO_MASK GENMASK(7, 0)
#define IPU7_IS_FREQ_CTL_DEFAULT_RATIO 0x1b
#define IPU7_PS_FREQ_CTL_DEFAULT_RATIO 0x14
+/* IS: 400MHz, PS: 400MHz */
+#define IPU8_IS_FREQ_CTL_DEFAULT_RATIO 0x10
+#define IPU8_PS_FREQ_CTL_DEFAULT_RATIO 0x10
/* D2D power control */
#define IPU7_BUTTRESS_REG_D2D_CTL 0x21d4
@@ -320,6 +323,7 @@ enum {
#define IPU7_BUTTRESS_OWN_ACK_IS_CLK BIT(9)
#define IPU7_BUTTRESS_OVERRIDE_PS_CLK BIT(2)
#define IPU7_BUTTRESS_OWN_ACK_PS_CLK BIT(10)
+#define IPU7_BUTTRESS_REG_PS_PLL_ENABLE 0x21bc
/* PB registers */
#define IPU7_GLOBAL_INTERRUPT_MASK 0x8
diff --git a/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c b/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c
index fecaff5ce032..d991f4d29e36 100644
--- a/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c
+++ b/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c
@@ -538,6 +538,128 @@ static struct ipu7_mmu_hw ipu7p5_isys_mmu_hwdata[] = {
},
};
+static struct ipu7_mmu_hw ipu8_psys_mmu_hwdata[] = {
+ {
+ .name = "PS_FW_RD",
+ .offset = IPU8_PS_MMU_FW_RD_OFFSET,
+ .zlx_offset = IPU8_PS_ZLX_FW_RD_OFFSET,
+ .uao_offset = IPU8_PS_UAO_FW_RD_OFFSET,
+ .info_bits = 0x20003a01,
+ .refill = 0x00002726,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU8_PS_MMU_FW_RD_L1_BLOCKNR_REG,
+ .l2_block = IPU8_PS_MMU_FW_RD_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU8_PS_MMU_FW_RD_STREAM_NUM,
+ .nr_l2streams = IPU8_PS_MMU_FW_RD_STREAM_NUM,
+ .l1_block_sz = { 0x00, 0x08, 0x0a, 0x0e, 0x10, 0x12, 0x14, 0x16,
+ 0x18, 0x18, 0x18, 0x18 },
+ .l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
+ 0x10, 0x12, 0x14, 0x16 },
+ .zlx_nr = IPU8_PS_ZLX_FW_RD_NUM,
+ .zlx_axi_pool = { 0x00000f30 },
+ .zlx_en = { 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 },
+ .zlx_conf = { 0x0, 0x2, 0x0, 0x0, 0x2, 0x2, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 },
+ .uao_p_num = IPU8_PS_UAO_FW_RD_PLANENUM,
+ .uao_p2tlb = { 0x2d, 0x32, 0x33, 0x30, 0x34, 0x35, 0x36, 0x31,
+ 0x0, 0x0, 0x0, 0x0 },
+ },
+ {
+ .name = "PS_FW_WR",
+ .offset = IPU8_PS_MMU_FW_WR_OFFSET,
+ .zlx_offset = IPU8_PS_ZLX_FW_WR_OFFSET,
+ .uao_offset = IPU8_PS_UAO_FW_WR_OFFSET,
+ .info_bits = 0x20003901,
+ .refill = 0x00002524,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU8_PS_MMU_FW_WR_L1_BLOCKNR_REG,
+ .l2_block = IPU8_PS_MMU_FW_WR_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU8_PS_MMU_FW_WR_STREAM_NUM,
+ .nr_l2streams = IPU8_PS_MMU_FW_WR_STREAM_NUM,
+ .l1_block_sz = { 0x00, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x10, 0x10 },
+ .l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e },
+ .zlx_nr = IPU8_PS_ZLX_FW_WR_NUM,
+ .zlx_axi_pool = { 0x00000f20 },
+ .zlx_en = { 0, 1, 1, 0, 0, 0, 0, 0 },
+ .zlx_conf = { 0x0, 0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0 },
+ .uao_p_num = IPU8_PS_UAO_FW_WR_PLANENUM,
+ .uao_p2tlb = { 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x0, 0x0, 0x0 },
+ },
+ {
+ .name = "PS_DATA_RD",
+ .offset = IPU8_PS_MMU_SRT_RD_OFFSET,
+ .zlx_offset = IPU8_PS_ZLX_DATA_RD_OFFSET,
+ .uao_offset = IPU8_PS_UAO_SRT_RD_OFFSET,
+ .info_bits = 0x20003801,
+ .refill = 0x00002322,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU8_PS_MMU_SRT_RD_L1_BLOCKNR_REG,
+ .l2_block = IPU8_PS_MMU_SRT_RD_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU8_PS_MMU_SRT_RD_STREAM_NUM,
+ .nr_l2streams = IPU8_PS_MMU_SRT_RD_STREAM_NUM,
+ .l1_block_sz = { 0x00, 0x04, 0x06, 0x08, 0x0c, 0x0e, 0x10, 0x14,
+ 0x18, 0x1c, 0x1e, 0x22, 0x24, 0x26, 0x28, 0x2a,
+ 0x2c, 0x2e, 0x30, 0x32, 0x36, 0x3a, 0x3c, 0x3c,
+ 0x3c, 0x3c },
+ .l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
+ 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
+ 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e,
+ 0x30, 0x32 },
+ .zlx_nr = IPU8_PS_ZLX_DATA_RD_NUM,
+ .zlx_axi_pool = { 0x00000f30 },
+ .zlx_en = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
+ .zlx_conf = { 0x6, 0x3, 0x3, 0x6, 0x2, 0x2, 0x6, 0x6,
+ 0x6, 0x3, 0x6, 0x3, 0x3, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x2, 0x6, 0x6, 0x3, 0x0, 0x0,
+ 0x0, 0x0 },
+ .uao_p_num = IPU8_PS_UAO_SRT_RD_PLANENUM,
+ .uao_p2tlb = { 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e,
+ 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
+ 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x0, 0x0,
+ 0x0, 0x0 },
+ },
+ {
+ .name = "PS_DATA_WR",
+ .offset = IPU8_PS_MMU_SRT_WR_OFFSET,
+ .zlx_offset = IPU8_PS_ZLX_DATA_WR_OFFSET,
+ .uao_offset = IPU8_PS_UAO_SRT_WR_OFFSET,
+ .info_bits = 0x20003701,
+ .refill = 0x00002120,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU8_PS_MMU_SRT_WR_L1_BLOCKNR_REG,
+ .l2_block = IPU8_PS_MMU_SRT_WR_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU8_PS_MMU_SRT_WR_STREAM_NUM,
+ .nr_l2streams = IPU8_PS_MMU_SRT_WR_STREAM_NUM,
+ .l1_block_sz = { 0x00, 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
+ 0x12, 0x14, 0x16, 0x18, 0x1c, 0x1e, 0x22, 0x24,
+ 0x28, 0x2a, 0x2e, 0x30, 0x32, 0x36, 0x38, 0x3a,
+ 0x3a, 0x3a },
+ .l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
+ 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
+ 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e,
+ 0x30, 0x32 },
+ .zlx_nr = IPU8_PS_ZLX_DATA_WR_NUM,
+ .zlx_axi_pool = { 0x00000f50 },
+ .zlx_en = { 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ .zlx_conf = { 0x3, 0x6, 0x38000002, 0x38000000, 0x3, 0x38000002,
+ 0x38000002, 0x38000002, 0x38000002, 0x38000002,
+ 0x38000002, 0x6, 0x3, 0x6, 0x3, 0x6,
+ 0x3, 0x6, 0x3, 0x3, 0x6, 0x3, 0x3, 0x0,
+ 0x0, 0x0 },
+ .uao_p_num = IPU8_PS_UAO_SRT_WR_PLANENUM,
+ .uao_p2tlb = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x00,
+ 0x00, 0x00 },
+ },
+};
+
static struct ipu7_mmu_hw ipu8_isys_mmu_hwdata[] = {
{
.name = "IS_FW_RD",
@@ -818,15 +940,10 @@ static const struct ipu7_mmu_hwdata ipu7p5_mmu_hwdata_lookup[IPU_SUBSYS_NUM] = {
},
};
-/*
- * IPU8 has no dedicated psys MMU table upstream (psys pipeline
- * support is not targeted for this driver); reuse the IPU7P5 psys
- * table as a placeholder so the psys bus device still initialises.
- */
static const struct ipu7_mmu_hwdata ipu8_mmu_hwdata_lookup[IPU_SUBSYS_NUM] = {
[IPU_PSYS] = {
- .hwdata = ipu7p5_psys_mmu_hwdata,
- .nr_mmus = ARRAY_SIZE(ipu7p5_psys_mmu_hwdata),
+ .hwdata = ipu8_psys_mmu_hwdata,
+ .nr_mmus = ARRAY_SIZE(ipu8_psys_mmu_hwdata),
},
[IPU_ISYS] = {
.hwdata = ipu8_isys_mmu_hwdata,
diff --git a/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h b/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h
index 5c552f4ae4f6..0d3fd7ddea64 100644
--- a/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h
+++ b/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h
@@ -277,6 +277,57 @@
#define IPU8_IS_MMU_NUM 5U
+/* PS MMU FW RD */
+#define IPU8_PS_MMU_FW_RD_OFFSET 0x148000
+#define IPU8_PS_MMU_FW_RD_STREAM_NUM 12
+#define IPU8_PS_MMU_FW_RD_L1_BLOCKNR_REG 0x54
+#define IPU8_PS_MMU_FW_RD_L2_BLOCKNR_REG 0x84
+
+/* PS MMU FW WR */
+#define IPU8_PS_MMU_FW_WR_OFFSET 0x149000
+#define IPU8_PS_MMU_FW_WR_STREAM_NUM 8
+#define IPU8_PS_MMU_FW_WR_L1_BLOCKNR_REG 0x54
+#define IPU8_PS_MMU_FW_WR_L2_BLOCKNR_REG 0x74
+
+/* PS MMU FW Data RD VC0 */
+#define IPU8_PS_MMU_SRT_RD_OFFSET 0x14a000
+#define IPU8_PS_MMU_SRT_RD_STREAM_NUM 26
+#define IPU8_PS_MMU_SRT_RD_L1_BLOCKNR_REG 0x54
+#define IPU8_PS_MMU_SRT_RD_L2_BLOCKNR_REG 0xbc
+
+/* PS MMU FW Data WR VC0 */
+#define IPU8_PS_MMU_SRT_WR_OFFSET 0x14b000
+#define IPU8_PS_MMU_SRT_WR_STREAM_NUM 26
+#define IPU8_PS_MMU_SRT_WR_L1_BLOCKNR_REG 0x54
+#define IPU8_PS_MMU_SRT_WR_L2_BLOCKNR_REG 0xbc
+
+/* PS UAO FW RD */
+#define IPU8_PS_UAO_FW_RD_OFFSET 0x156000
+#define IPU8_PS_UAO_FW_RD_PLANENUM 12
+
+/* PS UAO FW WR */
+#define IPU8_PS_UAO_FW_WR_OFFSET 0x157000
+#define IPU8_PS_UAO_FW_WR_PLANENUM 8
+
+/* PS UAO SRT RD */
+#define IPU8_PS_UAO_SRT_RD_OFFSET 0x154000
+#define IPU8_PS_UAO_SRT_RD_PLANENUM 26
+
+/* PS UAO SRT WR */
+#define IPU8_PS_UAO_SRT_WR_OFFSET 0x155000
+#define IPU8_PS_UAO_SRT_WR_PLANENUM 26
+
+#define IPU8_PS_ZLX_DATA_RD_OFFSET 0x14e000
+#define IPU8_PS_ZLX_DATA_WR_OFFSET 0x14f000
+#define IPU8_PS_ZLX_FW_RD_OFFSET 0x150000
+#define IPU8_PS_ZLX_FW_WR_OFFSET 0x151000
+#define IPU8_PS_ZLX_DATA_RD_NUM 26
+#define IPU8_PS_ZLX_DATA_WR_NUM 26
+#define IPU8_PS_ZLX_FW_RD_NUM 12
+#define IPU8_PS_ZLX_FW_WR_NUM 8
+
+#define IPU8_PS_MMU_NUM 4U
+
struct ipu7_mmu_hw {
char name[32];
--
2.43.0
next prev parent reply other threads:[~2026-09-30 9:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 9:01 [PATCH 0/7] media: ipu6: add IPU8 support Divyamani Tripathi
2026-09-30 9:01 ` [PATCH 1/7] media: ipu6: update ipu7 InSys ABI to 1.2.1.20251215_224531 Divyamani Tripathi
2026-09-30 9:01 ` [PATCH 2/7] media: ipu6: add IS_IPU8() macro Divyamani Tripathi
2026-09-30 9:01 ` [PATCH 3/7] media: ipu6: add IPU8 InSys ABI 1.0.14 support Divyamani Tripathi
2026-09-30 9:01 ` [PATCH 4/7] media: ipu6: make ipu7 gpreg stride configurable as per IPU version Divyamani Tripathi
2026-09-30 9:01 ` [PATCH 5/7] media: ipu6: add IPU8 isys chip/MMU enablement Divyamani Tripathi
2026-09-30 9:01 ` Divyamani Tripathi [this message]
2026-09-30 9:01 ` [PATCH 7/7] media: ipu6: add PCI ID for IPU8 Divyamani Tripathi
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